Abstract: Introduced briefly the ARINC429 main line and the HI-8582 chip’s characteristic, has given based on the HI-8582 ARINC429 main line design mentality and the method. Finally the union project gave the monolithic integrated circuit AT89C52 data to receive, to send the procedure example actually.
Key word: HI-8582, ARINC429 receive, ARINC429 transmission, AT89C52
1 ARINC429 main line and agreement chip HI-8582 synopsis
1.1 ARINC429 aviation main line synopsis
The ARINC429 main line is the civil aviation number bus transmission standard which US Aeroradio Company formulates, it had stipulated uses this main line’s aviation electronics’ information to flow with the ARINC429 master data character form. ARINC429 is the unidirectional transmission main line, the information can only from communication facility’s transmission mouth output, after transmits the main line to pass on to and its connected need this information other equipment’s mouth. When needs between two communication facilities the two-way transmission, respectively uses an independent transmission main line in each direction. The ARINC429 correspondence uses has the odd-parity check 32 information words, the information word through the product label recognition, most has 256 product labels. Uses the bipolarity nulling operation system the three states of matter code modulation system, namely the modulation signal three level condition modulation which by “high”, “zero” and “low” the condition is composed.
1.2 HI-8582 synopses
At present the ARINC429 main line agreement chip which uses in the board installation are many, comparatively, HOLT INTEGRATED CIRCUITS Corporation produces HI-8582 is a section of performance price quite high ARINC429 agreement chip. This component’s major function is as follows:
* conforms to the ARINC429 main line agreement;
* has the independent bidirectional receive and the transmission connection;
* does not need to actuate, but on direct ARINC429 main line;
* the product label may sequence distinguishes;
* the serial data speed may suppose the position is 100kbps or 12.5kbps;
* may carry on the odd and even condition verification to the receive data; And may to transmit the data odd and even condition to carry on the establishment;
* may from between the movable property unknown character and the character gap;
●52 the foot PQFP seal, saves the board space.
2 AT89C52 and HI-8582 connection designs
2.1 connection principle introduction
Because AT89C52 is 8 processors, but HI-8582 is 16 connection chips, used piece of CPLD in the connection design to realize the connection, in the design selects ALTERA Corporation’s EPM7128 to take the interface circuit. The electric circuit diagram see Figure 1.
In Figure 1, D1 is monolithic integrated circuit AT89C52, the P0 port uses in the data the exchange, the P2 port uses in controlling, uses outside two to interrupt 429 signals which INT0, the INT1 receive receives, monolithic integrated circuit’s reset signal is the hardware watch-dog produces, in Figure 1 has not drawn, reset signal RST takes CPLD the input signal, monolithic integrated circuit’s clock selects 12MHz, simultaneously 12MHz takes CPLD the clock source. D2 is CPLD component EPM7128, mainly completes 8 main lines and 16 main line’s transformations, the data exchange, arranges the decoding, to produce the HI-8582 clock and the reset signal. D3 is ARINC429 interface circuit HI-8582, BD00~BD11 is the bidirectional data bus and the EPM7128 docking, other are the discrete magnitudes.
2.2 CPLD control logics
Figure 2 interface circuit’s CPLD control logic
Figure 2 interface circuit’s CPLD control logic
The CPLD control logic see Figure 2. U12 is the reverser, monolithic integrated circuit’s reset signal reverse evacuation HI-8582 MR base pin, repositions in HI-8582 the register. U6~U11 constituted the frequency dividing circuit, divides into 1MHz the 12MHz clock rate, takes HI-8582 the clock signal. U1~U5 is the three states of matter 8D trigger, by the OE control output, CLK is the clock controlling, rises saves the data along the lock, the low level maintains, when OE is the high level the output is the high-resistance condition.
2.3 HI-8582 replacements and initialization
On after electric circuit electricity, the monolithic integrated circuit first repositions the RST base pin (high level effective), after simultaneously RST reverse, repositions HI-8582, then writes about the control word on 16 bit data main lines, hereafter then may receive and transmit the data. In ordinary circumstances, when both cannot receive when cannot transmit the data, should suspect the initialization process. The initialization routine is as follows:
CLR 7BH; CWSTR clear 0
MOV P0,2FH;
SETB P2.0;
CLR P2.0; The rise extends the lock to save
CLR P2.2; Establishes 8582 for the output pattern
MOV P0,#31H;
SETB P2.3; The rise extends the lock to save control word low 8
CLR P2.3;
MOV P0,#0E0H;
SETB P2.1; The rise extends the lock to save control word high 8
CLR P2.1;
SETB 7BH;
MOV P0,2FH ;
SETB P2.0; The rise extends the lock to save
CLR P2.0;
SETB P2.2; Establishes 8582 for the input pattern
2.4 HI-8582 data sending processes
When HI-8582 transmission data, first should set at the ENTX pin is the low level, sets at again PL1 lowly, will lower 16 bit data to write about on 16 bit data main lines, afterward, sets at high PL1, sets at again PL2 lowly, will be high 16 bit data to write about on 16 bit data main lines, after the data finished, set at high ENTX. The HI-8582 transmission memory are most may load 16 32 word lengths the data, what HI-8582 uses is advanced leaves the transmission order first. The calling order is as follows:
MOV R0,#0A0H;
CLR 7CH; ENTX sets lowly
MOV P0,2FH;
SETB P2.0;
CLR P2.0;
CLR 7EH; PL1 sets lowly
MOV P0,2FH;
SETB P2.0;
CLR P2.0;
CLR P2.2; Establishes 8582 for the output pattern
MOV A,@R0; Reads in 8 bit data
MOV P0, A;
SETB P2.3;
CLR P2.3;
INC R0;
MOV A,@R0; Reads in 8 bit data
MOV P0, A;
SETB P2.1;
CLR P2.1;
INC R0;
SETB 7EH; PL1 sets high
MOV P0,2FH;
SETB P2.0;
CLR P2.0;
SETB P2.2;
CLR 7DH; PL2 sets lowly
MOV P0,2FH;
SETB P2.0;
CLR P2.0;
CLR P2.2;
MOV A,@R0; Reads in 8 bit data
MOV P0, A;
SETB P2.3;
CLR P2.3;
INC R0;
MOV A,@R0; Reads in 8 bit data
MOV P0, A;
SETB P2.1;
CLR P2.1;
SETB 7DH; PL2 HIGH
MOV P0,2FH;
SETB P2.0;
CLR P2.0;
SETB 7CH; ENTX sets high
MOV P0,2FH;
SETB P2.0;
CLR P2.0;
SETB P2.2;
2.5 HI-8582 data receiving processes
After the receiver 1 receives the data, the system will set at the HF1 low level, but when the receiver 2 will receive the data, the system will set at HF2 will be the low level. Will want to cause the receiver 1 to receive the data the character 1 to deliver on to 16 bit data main lines, should set at SEL is the low level first, will then set at EN1 is the low level, then will again set at EN2 is the high level, SEL is the high level, then may 2 deliver the character to 16 bit data main lines. Must make the receiver 2 data to deliver to the bit data main line on, then sets at EN2 is the low level, EN1 is the high level then. The receive procedure is as follows:
CLR 7AH; Reads the data from FIFO
MOV P0,2FH; SEL sets lowly
SETB P2.0;
CLR P2.0;
CLR 78H; EN2 sets lowly
MOV P0,2FH;
SETB P2.0;
CLR P2.0 ;
SETB P3.3 ;
CLR P3.3 ;
CLR P2.6; Establishes 8582 low 8 inputs
SETB P2.7 ;
CLR P2.7; The lock saves 8582 low 8 inputs
MOV A, P0; Reads the 429 1st byte (8)
MOV R2, A; Preserved data
SETB P2.6; Establishes the first byte input for high-resistance
CLR P2.5; Establishes the second byte is the input
SETB P2.4;
CLR P2.4; The lock saves the 8582 second byte input
MOV A, P0; Reads the 429 2nd byte (8)
MOV R3, A; Preserved data
SETB P2.5; High-resistance condition
SETB 78H; EN2 HIGH
MOV P0,2FH;
SETB P2.0;
CLR P2.0;
SETB 7AH; SEL sets high
MOV P0,2FH;
SETB P2.0;
CLR P2.0;
CLR 78H; EN2 sets lowly
MOV P0,2FH;
SETB P2.0;
CLR P2.0;
CLR P2.6;
SETB P2.7;
CLR P2.7;
MOV A, P0; Reads the 429 3rd byte (8)
MOV R4, A; Preserved data
SETB P2.6; High-resistance condition
CLR P2.5; Establishes low 8 is the input
SETB P2.4;
CLR P2.4;
MOV A, P0; Reads the 429 4th byte (8)
MOV R5, A; Preserved data
SETB P2.5; High-resistance condition
SETB 78H; EN2 sets high
MOV P0,2FH;
SETB P2.0;
CLR P2.0;
The above procedure uses the interrupt receive data, when after HI-8582 FIFO full, HF1 or HF2 will become the low level, has the interrupt, had finished after the above program processing, HF1 or HF2 will become the high level, thus completes a time data the receive flow.
3 concluding remark
According to the method which this article introduced has succeeded realizes the HI-8582 ARINC429 aviation bus interface design, the design board installation batch equipment operating aircraft, the effect has been good.
Reference:
1 SZ-01 digital transmission system, HB6096-86, People’s Republic of China Aviation Ministry of industry standard.
2 HI-8582, ARINC 429 System on a Chip, HOLT INTEGRATED CIRCUITS.
3 MAX 7000 Programmable Logic Device Family Data Sheet, Altera Corporation.
