High grade, the low gear rate speech coding algorithm the status is getting more and more important in the modern communication system, is widely applied in such as IP telephone, pronunciation mailbox, domains and so on military wireless communication. In some special application domain, the channel bandwidth is very specially narrow moreover the error rate to be high, must realize the pronunciation communication on this kind of channel, the low speed and the low speed speech compression coding technology is the key really. Before as a result of the hardware condition’s limit, this kind of low gear rate arranges the decoding algorithm often only to be able complex to pause in the principle and the computer realizes the stage. Recent year, as a result of the VLSI technology’s vigorous development, the high performance digital signal processing chip’s DSP popularization, these encoding algorithm started the large-scale utilization realistic domain particularly. This design is arranges general for this set of military speech coding algorithm modular design one decodes the platform. This platform already did for the embedded low power loss pronunciation module, applies domains and so on speech coding and speech synthesis, and the small scale quantity has produced.
1. Pronunciation hardware platform overall introduction and system frame
This voice signal processes the platform to need to consider the following several aspects the design requirements. In the operand aspect, several kind of speech coding algorithm which in this platform moves has the quite high operation order of complexity, indicated after the CCS simulation test result, requests the DSP chip to have the 50MIPS handling ability at least. In the connection design aspect, embarked this sounder module the communication platform to define the connection base pin which as shown in Table 1, VIN and VOUT connected the communication platform separately on the microphone and receiver’s input and the output voice, PTT connected on microphone’s button, pressed down the PTT expression request telephone conversation. TXD and RXD respectively are the transmission and the receive digital pronunciation symbol stream signal, RTS and CD respectively are the transmission and the receive symbol stream instructed, for low level time expressed that the symbol stream is effective. TXC is system’s synchronized clock. In power loss aspect, because is the handhold equipment, the request uses the low power loss design, lengthens battery’s period of revolution. Moreover, the design system’s security is also the factor which needs to consider.
Table 1 hardware platform connection signal definition
Based on the above several design requirements, as well as before designs prototype system principle [7], we proposed one based on TMS320VC5510A2 and the MSP430F149 design proposal. [1] 5510A2 is the Texas Instruments company’s 55 series DSP most high-end product, this series’s DSP is aims at the handhold terminal device application situation design specially, under the same level condition its essence’s power loss is only 54 series DSP 1/3, and has a higher code to carry out the efficiency, its instruction also with 54 series mutually compatible, may very convenient carry on the code the transplant. 5510A2 highest digital signal’s handling ability is 200MIPS, can very good satisfy this platform to the operation request. [6]MSP430F149 is a section of extremely low power loss 16 RISC structure monolithic integrated circuit which the Texas Instruments produces, we use him to do for the master control chip are auxiliary DSP to complete the program load and the system encryption function. Figure 1 has given this hardware platform overall diagram.
Figure 1 the pronunciation processes the platform hardware architecture total diagram
Like the chart shows, when PTT is pressed down, then the expression request talks over the telephone, microphone input’s simulation voice VIN enlarges through an amplifying circuit inputs pronunciation CODEC in chip TLV320AIC11, TLV320AIC11 the modulus switch to transform afterward it 16bit the linear PCM form and transmits orally through DSP McBSP0 delivers the DSP interior receive pronunciation buffer, DSP in accumulates starts in the buffer data after certain frame size the encoding algorithm forming specific code rate the symbol stream. Composes the symbol stream is sent in another transmission bit class buffer cushion. In this buffer’s signal along is delivered in the synchronized clock TXC rise MODEM the modulation module to modulate and to launch. At the same time, DSP examines MODEM the CD signal, when CD signal effective (low level), in the synchronized clock TXC drop saves on RXD along the lock the data and sends in DSP the receive bit class buffer. When receives in a bit buffer the data accumulates to certain length, the DSP start decoding procedure it decodes the 16bit PCM pronunciation. This pronunciation is sent in through the McBSP0 mouth in TLV320AIC11, TLV320AIC11 the d/a converter to transform it the simulation the voice signal to send in the receiver.
Figure 2 CODEC chip and DSP, MCU hardware connection
The pronunciation CODEC chip and DSP, MCU hardware connection diagram as shown in Figure 2, [5]TLV320AIC11 is a section of pronunciation CODEC chip which the Texas Instruments company produces, it internal integrated A/D and a D/A module, and has the built-in operational amplifier, therefore only needs the very few parts to be possible connects the passive microphone and the receiver on AIC11. At the same time, because it may with TI Corporation’s DSP seamless connection. Like the chart shows, in this design the AIC11 work under principal-mode -like (M/S=1), under this pattern, the chip sampling rate is the SCLK foot input clock rate 1/256. The SCLK foot input’s clock originates from MCU P5.5, this base pin is the MCU vice-clock outputs is the MCU master clock 1/4. As a result of the MCU work in 4.096MHz, the CODEC sampling frequency is therefore 8KHz. AIC11 sends out the synchropulse by the 8KHz frequency on FS, and transmits DSP in the DOUT foot General 16bit PCM data stream. Meanwhile receives process decoding 16bit which from the DIN base pin DSP transmits the PCM pronunciation. Because has used AIC11, system’s use “agglutination logic” the part reduces greatly, thus effective reduction hardware circuit wafer area.
2. Hardware system encryption design
The effective protection intellectual property rights are the factor which the product development must consider. TI C55x the series DSP chip is one kind of open style bus structure, therefore harbors ulterior motives the human may visits and analyzes the DSP interior memory block through the JTAG connection and the corresponding software the code and the data, or is merely derives and duplicates these information directly, may steal the product easily. In view of this kind of realistic situation, the best solution is hands over the procedure by the chip producer mask enters in the chip internal ROM storage area, removes DSP again in the chip the JTAG logic module, the DSP internal main line and the outside isolates, like this is unable from exterior to obtain the internal information. However works as the product the output is not big, mask ROM in the cost is not realistic, needs seperately to try to find solution.
What this design proposed is one kind monolithic integrated circuit takes the hardware encryption part’s method based on TI Corporation MSP430F149. [6]MSP430F149 is TI production section of 16 RISC the structure Flash monolithic integrated circuit. Not only the power loss is extremely low, its other characteristic is its internal fuse Flash storage unit. When the performance history ended, after the procedure read in MSP430 internal Flash, if the exploiter might break friendly the Flash connection on the MSP430 main line’s friendly silk, after blowing a fuse, wants to visit its internal procedure and the data, must add on certain succession on monolithic integrated circuit’s JTAG pin the signal, entered the monolithic integrated circuit interior a section of BOOTSTRAP procedure, this BOOTSTRAP procedure request user read in 32 bytes to a password register in the password, if this password and read in the Flash specific position beforehand a password match case, could visit the internal procedure and the data resources, otherwise only could allow to carry on cleaning entire Flash the operation. Achieves the protection user program data code through this kind of mechanism the goal.
In view of the fact that the MSP430F149 internal data is unable to duplicate and the visit characteristic, we proposed one kind based on the MSP430F149 hardware encryption.
Figure 3 DSP and MSP430 hardware connection schematic drawing
Figure 3 is between MSP430 and DSP hardware connection schematic drawing [3]. Like the chart shows, this connection mode disposed DSP and MCU 16 multiplying connection pattern (HMODE=0), the data and the address shared the HD main line. HRW, HCNTL0 and the HCNTL1 different combination expressed separately to DSP EHPI mouth three register HPID (data), HPIA (address), HPIC (control) the read-write, concrete combination way as shown in Table 2.
Table under 2 multiplying patterns EHPI mouth read-write type instruction
The concrete encryption way summary is as follows:
1) is each circuit wafer assigns 128 keys, key’s choice to be completely stochastic, so long as the different board is not same then. (DES perhaps other encryption algorithm) the fever reads in MSP430 the key and the encryption algorithm the interior to do is DSP a boot procedure part.
2) uses this key and the encryption algorithm, after will encrypt the pronunciation to arrange the decoding algorithm the procedure and the data fever reads in DSP exterior to save in the Flash chip.
3) establishes DSP the work in HPI the mouth boot pattern, after each time restarts, the main engine was in the 0×10000 procedure space (in this section of BOOT procedure has contained a section of BOOT program loading reference decoding procedure), and 128 key load to DSP interior some specific position. The main engine sets at the DSP RST pin expressed high main engine’s load process ended. DSP starts the executive routine automatically from the 0×10000 position, this section of procedures read in has encrypted the procedure and the data from Flash, and uses the decipher procedure which the main engine reads in and unifies 128 keys to carry on the decipher, after the decipher procedure and the data is loaded into DSP in the procedure and the data segment starts the normal movement.
Because each circuit wafer corresponds to only 128 keys, therefore in DSP exterior Flash encrypts the procedure and the data do not have the significance completely regarding stealing secrets. This key and the decipher procedure is preserved in MSP430, therefore impossible to be stolen or the duplication. They only then the time which starts in the main engine only then passive voice load to DSP. The DSP procedure before starting carries out the normal decoding procedure to move section of procedures to cover this section of lood sector, therefore, stealing secrets is then unable to learn starts concrete operations.
4) the bit class pack bale breaking procedure will lay aside in MSP430. When code when in after DSP each receive pronunciation forming specific length bit class, approaches MSP430 to transmit an interrupt request. After receiving this request, MSP430 reads in this bit class through the DSP EHPI mouth, and adjusts between each bit position the order. After an adjustment bit class is returned to reads in DSP the transmission bit class buffer, and transmits MODEM according to the synchronized clock. Similarly, when the DSP receive bit class buffer receives full one, to the MSP430 transmission interrupt, MSP430 after receiving this interrupt through the EHPI mouth read-in receive bit class buffer in data, completes a bit location the rearrangement restoration.
This way may the effective guarantee code security as well as overall system’s secrecy. Regarding based on opened main line’s DSP system, this way was a very effective general hardware encryption.
Figure 4 MSP430 and DSP start software flow chart
3. Low power loss design
This hardware platform’s low power loss design embarks from three aspects, 1) chooses the low power loss the component. 2) full use chip low power loss pattern; 3) dynamic change chip movement frequency.
Selects the low power loss the component: This is saves the power loss the most direct way, present’s chip mostly through reduces the essence power line voltage to reduce the power loss, the present low power loss component’s power line voltage is smaller than generally 2V, TI DSP uses two kind of voltage actuations mostly, essence voltage 1.2-1.6V, I/O voltage 3.3V, this already can effective reduce the essence dynamic power loss, but can also give dual attention to I/O the level compatibility. TI Corporation’s MSP430 series MCU is also a section of power loss quite low component, under 3.3V, its normal work usually only needs several mW the power supplies, if establishes it IDLE or the sleep pattern pattern, its power loss will be lower. These are we choose one which of factors the component considers with emphasis.
Fully using chip low power loss pattern: the [4]5510A2 chip interior delimited five independent IDLE territories (Domain), was responsible for CPU, DMA, CACHE, the peripheral device, the clock generator, the EMIF connection disposition separately. Each territory may independent establish this territory jurisdiction many parts the active pattern or the IDLE pattern reduces by the DSP power loss. In view of this design, because has not used DMA, CACHE, in the clock generator three territory peripheral devices, therefore established these three territories the IDLE pattern. EMIF territory in DSP and MSP exchange data (to adjust a bit class which transmits and receive) time is set for the activity, when other is set is IDLE. Through such processing, has avoided the idle part in vain expended energy. [5]TLV320AIC11 may also independent is forbid A/D and the D/A part. When PTT has not pressed down, indicated that does not have the voice input, by now might a A/D mounted cylinder be the IDLE condition. Similarly, when MODEM CD signal to be high, does not express the effective digital symbol stream input sounder, therefore in this time may a D/A splitting be the IDLE condition. Through is treating this chip low power loss pattern operation, further reduced system’s power loss.
Dynamic frequency control: This method and basis forecast algorithm operand size, dynamic adjustment chip movement frequency, thus achieves saves the power loss the goal. Designs in this article in the platform moves three kind of low gear rate pronunciations arrange in the decoding algorithm, 600bps, 1200bps, the 2400bps peak value operand respectively is 37.4MIPS, 59.2MIPS, 44.8MIPS, therefore establishes separately the DSP operating frequency in 40.096MHz, 65.536MHz, 49.152MHz. The experiment proved that like this processes can reduce DSP very effectively the essence power loss.
4. Subtotal
This platform has the formidable voice signal handling ability, low characteristics and so on power loss as well as encryption. The practice proved that this platform has achieved the original these project objective completely in its application situation, has the broad application prospect.
Reference:
[1]TMS320VC5510AI DataSheet(sprs076I); TI corporation; April 2004
[2]Using the TMS320VC5510 Bootloader (spra763a); TI corporation; Mar 2002[3]TMS320VC5510 DSP Host Port Interface (HPI) Reference Guide (spru588a); TI corporation; Feb 2004
[4]TMS320C55x DSP Peripherals Overview (spru317g); TI corporation; Feb 2004
[5]TLV320AIC11 DataSheet(slws100); TI corporation; April 2002
[6]MSP430F14x familiy Mix Signal Microcontroller DataSheet (slas272); TI corporation; Aug 2004
the [7] low power loss general pronunciation processes the platform the design to realize; Lu Xiyu, Zhan is outstanding, Tang elder brother, Cui Huijuan; Miniature machine and application; 2005.7
