Introduction
The milliardfold ethernet passive light network (EPON) is one kind of point-multipoint topology light access network technology, uses the passive light component connection bureau end and the far-end equipment, realizes the ethernet service transparent transmission, and can realize synthesis service and so on pronunciation, video frequency in the identical construction turning on. EPON takes the emerging access network technology the prominent superiority to lie in the low cost, easy to maintain and the extension is good. The EPON system constitutes by OLT and ONU.
ONU hardware system design
System hardware by embedded control module and network exchange module two parts of constitutions. The embedded control module is the ONU control and the management core, it provides the hardware platform for the embedded Linux operating system’s movement, realizes through it to the network exchange module control and the disposition, realizes the network exchange module normal operation. The network exchange module provides the ether frame the exchange and the repeater function, the embedded control module carries on the correspondence through the PCI main line and the network exchange module, the access network exchange module interior various chips register, carries on to various chips disposes and gains each chip status messages. Network exchange module internal exchange chip BCM5615 the embedded control module visit to its, transforms into oneself visit to network exchange module interior various chips, has like this realized the embedded control module to the network exchange module interior various chips management.
Embedded control module connection design
Embedded processor MPC8245 synopsis
MPC8245 exceeds the allowed figure the quantity architecture PowerPC processor essence constitution by a peripheral device logic block and 32. Integrated a PCI bridge, DUART, the memory controller, the DMA controller, the EPIC interrupt controller, a news unit and a I2C controller in the peripheral device logic block. The processor essence support floating point calculation and the memory management, have the 16KB instruction high speed buffer (cache), 16KB data cache and power source management characteristic. MPC8245 contains a peripheral device logic main line, uses in connecting the processor essence and the peripheral device logic block. The processor essence may work under many kinds of different frequencies. MPC8245 already may serve as PCI host, may also serve as the PCI proxy controller. The support reaches 2GB much SDRAM; Supports 1~8 group of 4MB, 16MB, 64MB, 128MB, or 256MB memory.
Clock circuit
MPC8245 input clock by 33MHz the crystal oscillator passes the zero crossing time delay buffer to produce four group clock signals, a group takes MPC8245 the PCI main line clock and the essence input clock, system clock signal OSC_IN has not used, needs to earth. MPC8245 pin PLL_CFG[0:4] uses in disposing the frequency multiplication factor, passes through the internal frequency multiplier, produces the SDRAM clock and the 166MHz CPU essence clock. A group takes RTL8139 the PCI main line clock, a group takes BCM5615 the PCI main line clock.
PCI bus interface
The PCI main line work in 33MHz, in the design needs to guarantee that the PCI clock’s clock phase displacement is smaller than 2ns, otherwise, the system is possibly unable the normal work. MPC8245 as the PCI main processor, RTL8139 and BCM5615 REQ#, the GNT# distinction company arrives at MPC8245 REQ[0:1]#, GNT[0::1]#, realizes main line’s arbitration by MPC8245. Using address wire AD31, AD30 decided RTL8139, BCM5615 IDSEL, realize when the PCI main line disposition visit to RTL8139, BCM5615 selecting patches or strips of land as worth saving for seed. This method will make AD31, AD30 on-line to increase a load, therefore theirs IDSEL through the 1K resistance coupling to AD31, AD30 will come up the question which the solution load will aggravate. The PCI main line’s control signal requests to have pulls the resistance, guaranteed them, in has not actuated the equipment to actuate in main line’s situation still to have the stable value, thus FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR# and PERR# these signals use in the 10K resistance to pull.
Flash
In MPC8245, ROM/Flash is divided into 2 BANK, the BANK0 address is 0xFF800000~0xFFFFFFFF, selects patches or strips of land as worth saving for seed is /RCS0, RCS0 meets the memory code the memory to select patches or strips of land as worth saving for seed; The BANK1 address is 0xFF000000~0xFF7FFFFF, selects patches or strips of land as worth saving for seed is /RCS1. ROM/Flash/SRAM work when different data width (8, 16, 32, 64) under address bus, replacement, MPC8245 pin MDL0, /FOE decision log-on data bit width; After the replacement, the hardware repositions the disposition character determination data the width.
In this design chooses 512KB Flash to take the Bootloader code memory, the system work in 8 patterns, the corresponding address is 0xFF800000~0xFF87FFFF. Selects two piece of AM29LV320B respectively as the Bootloader/Linux essence and the file memory, AM29LV320B is 32 Mb, the list 3.3V power source power supply dodges saves, the programming and scratches writes the voltage by the internal production, dodges with the JEDEC single power source saves the standard to be compatible; May compose 4M×8Bit or 2M×16Bit memory. The available standard EPROM programmer carries on the programming; The access time most is short is 70ns; Independent selects patches or strips of land as worth saving for seed (CE#), to write enables (WE#) and the output enables (OE#) to control, may reduce to main line’s pressure. Selects patches or strips of land as worth saving for seed RCS1, RCS2 respectively to choose the Flash correspondence address which two piece of Flash, RCS1 selects is the Flash address which 0xFF000000~0xFF3FFFFF, RCS2 selects by the programming decision.
Jumps line J1 to use for RCS0 to receive Flash1, RCS1 to receive Flash0, like this after Bootloader code movement, the Bootloader code, the Linux essence code burns Flash1, saves piece of 512KB Flash, simultaneously leaves behind RCS2, RCS3 to select patches or strips of land as worth saving for seed the signal, remains does later expands Flash to use.
SDRAM
32MB SDRAM is composed of two piece of HY57V283220T. The MPC8245 SDRAM connection uses one to select patches or strips of land as worth saving for seed signal CS1, simultaneously takes two piece of HY57V 283220T selecting patches or strips of land as worth saving for seed, constitutes 64 bit data SDRAM. HY57V283220T is 4 Bank×1M×32Bit CMOS SDRAM, the list 3.3±0.3V power source power supply, all pins and the LVTTL connection are compatible, all inputs and the output take system clock’s rise along as the references.
CONSOLE and EMS interface circuit
The serial communication realizes through the MAX232 chip, works in the 3.3V working voltage, its volume is quite small, the work is stable. May realize through the serial port to the ONU network management. Uses commonly used PHY chip RTL8139 to expand a 10Mbps net mouth, causes after the Bootloader code homing system, downloads the Linux essence code through this net mouth, after systems operation, carries on the WEB management through this net mouth to ONU.
Exchange module connection design
The ethernet exchange module by 1 BCM5615 exchange chip, 3 BCM5228B the PHY chip, 1 BCM5221PHY chip, 1 HDMP-1636A milliardfold SERDES and the SDRAM chip is composed. This module provides 1 milliardfold light mouth (1000BASE-LX), 25 100,000,000,000,000 light mouths (100BASE-FX), realizes the ONU function hard core. A milliardfold mouth takes PON the receive port, receives the OLT broadcast transmission the data packet; Another milliardfold mouth connects 100,000,000,000,000, takes PON the transmission port, to OLT transmission data, what this port launches is the special wave length light. Realizes ONU and the OLT connection through the special exchange mechanism.
BCM5615 chip synopsis
BCM5615 integrates the multi-layered exchange chip, is the ethernet exchange module core. It has 24 10/100Mbps and 2 10/100/1000Mbps ethernet mouth; Has 2 and 3 exchanges and 2~7 filtration functions; May realize the entire line speed exchange, the exchange speed amounts to for 6,700,000 packages of/seconds; Supports IEEE 802.1Q.D; Has a 256KB internal data package of memory, may use SDRAM to expand the 64MB exterior data packet memory.
This design selects 3 piece of BCM5228B to provide 24 PHY ports. BCM5228B is the physical level component, the monolithic intension contains 8 independent PHY (port). BCM5615 manages 3 BCM5228B through the serial MII management connection the chip 24 PHY ports, the system is on the BCM5615 serial MII management connection operation realizes visit to BCM5228B through the transformation. BCM5228B each PHY port’s management address by PHYADD[4::0] pin establishment, if BCM5228B PHYADD[4::0] is PHYAD, then each piece of 8 ports correspond the management address respectively is ADDR=PHYAD PORTX, PORTX is each PHY port’s serial number.
Clock circuit
The BCM5615 core nuclear clock by the 133MHz crystal oscillator production, when designs PCB, should as far as possible approach BCM5615 the clock input pin, the BCM5615 GMII clock and the MII clock is 125MHz, by 125MHz crystal oscillator after the 74LCX245 cushion produces four group 125MHz clock sources, inputs to the BCM5615 GMII_CLKIN pin and 3 piece of BCM5228 REF_CLK pin. The attention connects BCM5228B the clock line to wait to be long, no matter milliardfold mouth whether to use, the GMII_CLKIN clock must provide.
System reset electric circuit
The system reset electric circuit uses the IMP811 replacement chip, after the 74LCX245 cushion produces the multi-channel reset signals, receives each chip separately the replacement pin. To reposition reliably, the request reset signal’s rise along cannot have the oscillatory occurrences occurrence.
System software design
This article chooses Linux to take the operating system, uses software development package SDK which Broadcom Corporation provides to develop BCM5615 the driver. PPCBOOT is the independence in other softwares, it is only responsible for the initialization and disposes the related hardware, then transfers the Linux essence reflection pilot operation systems operation, other softwares divide into the user space procedure and the essence space procedure two major parts. In the essence space operation embedded Linux operating system, the BCM5615 driver, the RTL8139 network mouth driver, realizes the STP STP essence module, hypothesized equipment VND which and VCD designs for the convenience entire software system and realizes uses. Between them the connection relations are: Linux provides essence API to give the BCM5615 actuation and other Linux may the dynamic load essence module, like STP, VND, VCD, RTL8139 network card actuation and so on.
ASIC actuation
The ASIC actuation is mainly completes to the BCM5615 initialization and the disposition work, and serves for the upper formation provides the connection. And the SAL level’s goal is each kind of service mapping which provides the operating system for driver’s API. Second is an intermediate level, may also say that is the entire driver core level, it establishes above SAL, its project objective is mainly provides the first floor register and memory’s visit, the PCI main line operation, the DMA operation as well as the interrupt processing function and so on. Driver’s top layer is the API level, it establishes above the DRV level, is to the DRV related part seal, thus provides each kind of service for the upper formation other software module, other modules through transfer this function to visit and to control ASIC. The ASIC actuation provides API is unable to the user advancement to transfer directly, therefore this article has designed a hypothesized character equipment (TTY), and compiles its driver, simultaneously orders the character equipment document which under the /dev table of contents with mknod the establishment corresponds.
To the operating system, the BCM5615 26 ports corresponds to a physical PCI equipment, namely ASIC, they share a PCI channel and the address space. This brings many for these with the network equipment close related software troublesome, therefore may design 26 ports 26 virtual network equipment (VND) and compiles its driver. Therefore, SNMPD and the spanning tree agreement software saw what is 26 hypothesized network cards, and does not have the difference with the ordinary network card.
Conclusion
This article uses the EPON system which the wavelength division multiple access (WDMA) realizes, compares with the similar products, has realizes, the performance good, easy to promote simply, the system construction cost low superiority, already obtained the important application in the broadband access network.
Thank you so much for the information. It is really helpful…