Introduction
ENC28J60 is 28 pin independent ethernet controller which Microchip Technology (American micro core science and technology company) the near future will promote.
Before then, the embedded system development may elect the independent ethernet controller is for the personal computer system design, like RTL8019, AX88796L, DM9008, CS8900A, LAN91C111 and so on. These component structure is not only complex, the volume is huge, and is quite expensive. At present in the market the majority of ethernet controller’s seal surpasses 80 pins, but conforms to IEEE 802.3 agreement ENC28J60 only then 28 pins, both can provide the corresponding function, and may simplify the related design greatly, reduces the space.
Figure 1 ENC28J60 hardware connection
1 structure and function
Below uses field standard serial peripheral device connection (SPI) ethernet controller ENC28J60 to have the chief feature:
◆ conforms to the IEEE 802.3 agreements. The built-in 10 Mbps ethernet physics level component (PHY) and the media visit controller (MAC), may receive and dispatch the information packet data reliably according to the field standard ethernet agreement.
◆ has the programmable filtration function. Special filter, including Microchip programmable pattern matching filter, but appraises, the receive automatically or refuses to accept Magic Packet, the unicast (Unicast), broadcasts (Multicast) or the broadcast (Broadcast) the information packet, reduces the master control monolithic integrated circuit’s processing load.
◆ 10 Mbps SPI connection. The field standard’s serial communication port, causes to lower also has the network connections function to 18 pin 8 monolithic integrated circuits.
◆ programmable 8 KB twin port SRAM buffer. Carries on the information packet by the highly effective way the memory, the retrieval and the revision, reduces the master control monolithic integrated circuit’s memory load. This buffer storage has provided the nimble reliable data management mechanism.
2 hardware designs
The ENC28J60 hardware design needs to pay attention to the reset circuit clock oscillator, the oscillator starts the timer, the clock output pin, the transformer, the terminal and other exterior component, input/output electricity equality several aspects. (Figure 1 may supply reference)
2.1 reset circuits
ENC28J60 has the electricity replacement (Power-on Reset) the function, on the RESET pin low level causes ENC28J60 to enter the replacement pattern; The RESET pin interior has weakly on pulls the resistance. ENC28J60 hardware connection as shown in Figure 1.
2.2 clock oscillators
ENC28J60 needs 25 MHz the crystal oscillator, meets in OSC1 and on the OSC2 foot; May also actuate by the external clock signal. This time 3.3 V external clock meets on the OSC1 foot, the OSC2 separation or reduces the system noise through a resistance earth.
2.3 oscillators start the timer
The ENC28J60 interior has an oscillator to start clock OST (Oscillator Start 瞮 p Timer), on the electricity 7 500 clock cycles (300 μs), after OST expires, the internal PHY side can the normal work. By now could not transmit or the receive text. The superior machine may through examine ENC28J60 internal ESTAT in register’s CLKRDY position condition to decide whether can establish the transmission or the receive text.
What needs to pay attention, when on ENC28J60 the electricity replacement or awakens from the PowerDown pattern, whether can examine ESTAT in register’s CLKRDY setting. Only then after CLKRDY setting, can transmit, the receive text, the visit related register.
2.4 clock output pin
The CLKOUT pin may provide the clock source for system’s in other equipment. After on electricity, the CLKOUT pin maintained the low level, after the replacement had finished, OST counting. After OST expiration, the CLKOUT output frequency is 6.25 MHz clocks.
The clock output function forbids through the ECOCON register, to adjust and to enable. The clock outputs may establish is 1, 2, 3, 4, 8 frequency divisions, after on electricity, the default is 4 frequency divisions. After ECOCON register disposition change, the CLKOUT pin has 80~320 ns detentions (maintains low level), then according to hypothesis output fixed frequency clock signal.
On the software or the RESET pin’s reset signal will not affect the ECOCON register’s condition. The PowerDown pattern will not affect clock’s output. When forbids the clock outputs, the CLKOUT pin maintains the low level.
2.5 transformers, terminal and other exterior component
In order to realize ethernet connection ENC28J60, needs several standard exterior component: Pulse transformer, bias resistance, storage capacitor and decoupling electric capacity.
The differential input pin (TPIN /TPIN-), needs one 1∶1 changes the ratio the pulse transformer realizes 10BASET. The difference output pin (TPOUT /TPOUT -), needs one changes the ratio is 1∶1, the belt center tap’s pulse transformer. The transformer needs to have 2 kV or higher isolation ability, against static electricity. Please refer to the chip handbook 16th chapter to transformer’s detail requirement “the electrical specification”. Each part needs after 2 50 OMEGA, the precision is 1% resistances and 1 0.01 μF electric capacity series earths.
What the author uses is Zhongshan Chinese kind company’s integrated ethernet insulating transformer RJ45 plug HR901170A.
All power supply pin (VDD, VDDOSC, VDDPLL, VDDRX, VDDTX) must meet on the exterior identical 3.3 V power sources; Likewise, all places (VSS, VSSOSC, VSSPLL, VSSTX) must meet outside identical ground. Between each power supply pin and the place must meet 1 0.1 μF ceramic electric capacity decoupling (electric capacity to as far as possible close power supply pin).
The actuation twisted pair line connection needs the big electric current, therefore the power line should extend as far as possible, is as far as possible short with the pin connection, reduces the power line interface resistance the consumption.
2.6 input power output
ENC28J60 is a 3.3 V CMOS component, but it designs easily to unify to 5 V systems in: SPI, CS, SCK, the SI input and the RESET pin is the same, may withstand 5 V voltages. When SPI and the interrupt input is incompatible with 3.3 V actuation’s CMOS outputs, possibly needs an unidirectional level switch. 74HCT08 (four AND gates), 74ACT125 (four three states of matter buffers) and many have the level switch which TTL the level input’s 5 V CMOS buffer chip may provide needs.
2.7 LED dispositions
LEDA and LEDB pin when replacement supports the polar automatic detection. Both may direct drive LED, and may fill the electric current actuation. When replacement ENC28J60 examines LED the connection, and defers to the PHLCON register’s default setting to actuate. In movement process LED polarity inversion after next subsystem replacement can examine. The LEDB connection is quite special, examines its connection in the replacement process, how decides initialization PHCON1 register’s PDPXMD position. If LEDB direct drive LED, then the PHCON1.PDPXMD position is reset, PHY work in half-duplex pattern; If LEDB absorbs the reverse electrical current to lighten LED, then PHCON1.PDPXMD by setting, PHY work in full-duplex pattern; If LEDB has not connected, then after the PHCON1.PDPXMD replacement’s value is indefinite. By now the master-control unit must establish this suitably, causes PHY to work in the condition which needs (half-duplex or full-duplex).
3 software interfaces
3.1 SPI connections
The SPI connection (Serial Peripheral Interface) is one kind of synchronized, the full-duplex serial interface, based on the host from the disposition, is 4 connections - - advocates/from enters (MOSI), the host enters/from leaves (MISO), serial clock (SCK), from machine choice (SSEL).
May have many main engines or from machine, but the identical time can only have a main engine and on the identical main line from machine can carry on the correspondence. In a data transmission process, the data is the synchronization carries on the transmission and the receive: The main engine to from machine the transmission 1 byte data, from machine also returns to 1 byte data to the main engine. The data transmission is in principle the full-duplex; But in fact, in the majority situations only then in a direction’s data stream contains the meaningful data.
The SPI form’s principal characteristic is the SCK signal invalid condition and the phase, the data transmission clock provides by the main engine. The commonly used clock establishment based on clock polarity (CPOL) and the clock phase (CPHA) two parameters, CPOL defines the SPI serial clock’s active state, but the CPHA definition is opposite from machine the output data position clock phase. CPOL and the CPHA establishment has decided the data sample clock along.
Is decided is different with CPOL and the CPHA establishment, SPI altogether has 4 kind of patterns, like Table 1 arranges in order.
Table 1 SPI 4 kind of patterns
3.2 ENC28J60 and monolithic integrated circuit’s connections
ENC28J60 is realizes with the micro controller MCU connection through SPI, supports 10 Mbps. Regarding does not have the SPI connection chip to be possible through to use the I/O mouth to simulate the SPI connection the way to realize. ENC28J60 only supports the SPI pattern 0,0.
The micro controller may through the SPI connection routing directive, visit ENC28J60 the register or the read-write receive/transmission buffer, completes the related operation. The replacement may also realize through the SPI connection by the software, the software repositions does not affect the RESET pin the condition.
ENC28J60 has two interrupt outputs, uses in event interrupt triggering and the network separately awakens the main engine.
CPU uses LPC2138 to realize the SPI mouth read-write operation with the great definition. SOSPDR is the SPI data register, this bidirectional register is SPI provides the transmission and the receive data, transmits the data through to write this register to provide, the SPI receive’s data may from this register reading. SOSPSR is the SPI condition register. In carries on the operation before the SPI connection must to its initialization. Below gives reads/writes the SPI connection the source code.
#define READSPI (Val)
{
S0SPDR = 0×00;
while (0 == (S0SPSR & 0×80));
Val = S0SPDR;
}
#define WRITESPI (Val)
{
if (0 == (S0SPSR & 0×40)) {
S0SPDR = Val;
while (0 == (S0SPSR & 0×80));
}
}
Also available LPC2138 SSP connects ENC28J60, must its establishment be the SPI pattern. Must note SSP to have 8 to receive/sends FIFO, if will process improper will create reads/writes the mistake. Because the buffer existence possible to destroy reads/writes ENC28J60 the succession.
Regarding does not have the SPI connection monolithic integrated circuit to be possible to use the ordinary I/O mouth simulation the method to realize the SPI main engine. This time must pay attention to when the static state clock’s invalid condition and the phase, as well as the output data position appears time; To ENC28J60 operation period selects patches or strips of land as worth saving for seed must maintain effective (low level), after the operation had ended, returns to the low level. Reads according to ENC28J60/writes the profile to be very easy to write simulates the SPI main engine’s procedure. The author once realized on AT89S51 has simulated the SPI main engine to read/writes MCP2515 the operation.
4 conclusions
The author has realized the ethernet correspondence in the LPC2138 ENC28J60 HR901170A platform. Is opposite in other plans, this system simplifies extremely. Regarding has not opened main line’s monolithic integrated circuit, although has the possibility to select the simulation parallel main line’s method to connect other ethernet controller, no matter but from the efficiency or the performance, was inferior that or uses the general I/O mouth with the SPI connection to simulate the SPI connection to connect ENC28J60 the plan.
May see, ENC28J60 has the characteristic extremely the independent ethernet controller: The SPI connection enables the small monolithic integrated circuit also to have the network connections function; Integrates MAC and PHY does not need other peripheral devices; Has the programmable filtration function, but appraises, the receive automatically or refuses to accept the multiple message packages, reduced the master control monolithic integrated circuit’s processing load; The interior inherits programmable 8 KB the twin port SRAM buffer, the operation nimble convenient. The deficiency to only support 10BASET.
Reference
[1] Microchip Technology Inc. ENC28J60 StandAlone Ethernet Controller with SPI Interface. http://www.microchip.com/.
[2] Philips Semiconductors. LPC213x User Manual. http://www.philipsmcu.com/.
[3] the week render meritorious service, opens China, and so on. Explains the profound in simple language ARM7–LPC213x/LPC214x (first book). Beijing: Beijing University of Aeronautics and Astronautics Publishing house, 2005.
