Abstract: This article introduced the MVB main line frame structure, and completed has used in the network connections the MVB main line visiting the IP nucleus the design. Based on the SOPC design concept, this article through Quarters II software platform’s SOPC the Builder design tool, integrates the NiosII soft nuclear processor and the main line visits the IP nucleus, realized has satisfied the MVB agreement I kind of network card design.
Key word: Train communication network (TCN); MVB; The main line visits IP nucleus (BAP); SOPC; NiosII
The domestic and foreign vehicles carry the networking the development are develop along with the field bus networking development, has produced RS485, Lonworks, WorldFIP successively and so on many kinds of main line network form. in 1999, international electrician committee (IEC) has promulgated the IEC-61375 standard, in this standard carries the vehicle the network to divide into two level of main line’s hierarchical structures, namely uses in connecting various to be possible between dynamic grouping stranded wire type train main line WTB vehicles’ (Wire Train Bus) and uses in connecting the vehicles (or fixed grouping vehicles unit) internal each kind of equipment’s multi-purpose vehicles main line MVB (Multifunction Vehicle Bus), between them the train main line node is playing gateway’s role, the MVB network as a result of the low request and its usability high characteristic, utilizes in reality is very widespread. This article through the deep research several kind of train communication network product first floor agreement, specially the TCN first floor agreement and the key technologies, based on the SOPC design concept, designs conforms to IEC-61375 the standard MVB main line to visit IP (Intellectual Property) the essence and the network card.
System architecture
This design is precisely based on the SOPC thought that the development realizes proprietary intellectual property rights MVB the receiving and dispatching controller IP nucleus, with the aid in the Quarters II development kit, integrates to Altera in the FPGA component, constructs on the SOC piece the system to realize the MVB network card basic function, compares the traditional overseas MVB network card, simplified system’s structure greatly, reduced the development difficulty.
The traditional MVB network card’s hardware architecture is quite complex, the design realizes on has the great difficulty. As shown in Figure 1, is Duagon Corporation’s section of typical MVB the network card d113 hardware architecture. Its hardware mainly has the following several part constitution: The central controller uses the high performance 32 ARM processor, the memory system by non-volatility program memory (ROM)Flash, as well as data-carrier storage RAM composes, on the programmable component realizes the MVB transceiver as well as the exterior PC/104 bus interface.
Figure 1 d113 hardware diagram
This design on piece of FPGA, uses the MVB network card which the SOPC technology realizes: 32 high performance soft nuclear processor NiosII which provides by Altera Corporation substitutes for the ARM processor, ROM, RAM and Traffic Memory may internal tool realize in FPGA by SOPC the Builder, integrates the MVB main line to visit the IP nucleus again then to be possible to constitute the MVB network card, has realized on the genuine piece the system. Its hardware diagram as shown in Figure 2.
Figure 2 network card structure diagram
The main line visits the IP nucleus realization
The main line visits the IP nucleus is realizes WTB and the MVB main line visit processor (BAP) central content. From the IP nucleus union physics level’s main line transceiver completes the main line visit. The main line visits the IP endorse to divide into the physical level, the data link layer and the application layer connection three major parts. 1) realizes baseband Manchester Biphase-L in the physical level to arrange the decoding, medium redundancy processing, the medium installs the unit interface; Uses in inputting the decoding the digital phase-locked loop design. 2) link level including addressing system, F-code (function code) production, main from equipment frame content packing, medium access control (MAC) and so on. 3) usually uses shared buffer memory’s method with the application layer connection, needs to complete port’s definition and the maintenance, corresponds memory’s control and so on. Its functional block diagram like chart 3.
Figure 3 network card structure diagram
MVB frame structure
Has two kind of frame forms in MVB, one kind is can only the main equipment frame which transmits by the main line main equipment, is called the main frame, one kind is to respond the main frame, but by transmits from the equipment from the equipment frame, is called from the frame. A frame starts by 9 delimiters, main equipment frame dividing line Fu Hecong the equipment frame dividing line symbol to prevents the synchronized defeat is not same.
MVB encoder
Not only the MVB main line data take the frame as the Fundamental unit, the data frame has used Manchester code transmission, the code and the decoder carries on Manchester to arrange the decoding, the frame frame tail arranges the decoding also to need specially to carry on here, uses traditional Manchester codec encoder-decoder to be unable to complete this work. In this design, used the union transceiver state machine concrete condition to carry on arranges the decoding the design method to solve this problem. The MVB frame transmitter transfers Manchester through the control logic module to code and CRC verification module, the correspondence memory cell module completes the buffer data the transmission.
MVB frame receiver
The receiver realizes the key is the valid data frame recognition, realizes the mentality to be similar to the transmitter, may realize according to the code verification. Another question is with main line’s connection way, this design has used 8 bit parallel data width output, adds serial number marking the method to be possible to receive assigns the length willfully the valid data.
Data check
The frame data protects with or the more 8 bit check sequence, the data content should process 64 coded words (to use 16 or 32 to small some data), not including outset dividing line symbol and termination dividing line symbol. This coded word and afterward verification sequence should take the highest effective data position first to transmit.
Verification sequence according to by its protection 16,32 or 64 bit data cyclical redundancy check (CRC) computations. The verification sequence according to the multinomial computation, 7 operation results verifies the position with a partner to carry on the expansion. All 8 bit data take the counter-transmission.
Correspondence memory cell module
The correspondence memory (Traffic Store) takes in the MVB standard to realize the method importantly, is in the MVB connection network card’s important component. The correspondence storage capacity’s size basis concrete application decides. The correspondence storage capacity which usually needs in the MVB network is 32 or 64 ports then, each port needs to take the space is 256 most greatly, like this corresponds the space which the memory needs is 8kbits or 16kbits. Opens in FPGA DRAM to take the correspondence memory cell, completes the data interactive function. Uses for to save the data which transmits by way of the MVB main line, is control logic module and between the code verification unit shared cell. The control logic module basis correspondence storage module port address’s start address, as well as its data length, reads the corresponding process data and the news data and so on.
Avolon bus interface design
The MVB main line processes the IP nucleus and NiosII connection design realization is (shares RAM) through Traffic Store to realize. Uses Quarters ⅡMegaWizard plug-in the Manager tool has a pair of mouth RAM module, its establishment as shown in Table 1.
This correspondence memory and the Nios II processor pass the Avalon bus interface.
On SOPC piece system MVB network card’s realization
The main line visits the IP nucleus and the Nios II system integration
Tool we integrated the NiosII soft nuclear processor, 4k internal RAM, the MVB main line using Quarters II SOPC the Builder to visit the IP nucleus (including encoder and decoder) as well as the LCD control module, constituted one to be able to realize on a MVB kind of network card function piece the system.
Software design
SOPC system which states based on above, we designed a basic MVB node to realize the process data transmission. This node establishes the 0×14 address as the source port, when main frame polling 0×14 address, this node packs Cheng Congzheng this port’s in data to transmit to the main line above, sleeps the port by the refurbishing 0×14 address.
the altera_avalon_mvb.h design, visits the IP nuclear register read-write including the main line the great definition.
#define IORD_ALTERA_AVALON_ MVB_SENDREG(base) IORD (base, 0)
#define IOWR_ALTERA_AVALON_ MVB_SENDREG (base, data) IOWR (base, 0, data)
Sets at the MVB main line receive permission position in the main function, the circulation waited for that receives main frame which the MVB master-control unit sends. The node after receiving the main frame, the procedure enters the interrupt handling routine. Withdraws in the main frame port address which in the interrupt routine receives, and carries on the comparison with own preinstall’s port address, if address match case, then the node sends to this port’s data through the MVB transmitter on the main line, realizes the port data refurbishing operation.
The simulation and realizes
Simulation profile
In this experiment, has carried on the function simulation and the FPGA confirmation to the laboratory design’s MVB board card, through has confirmed the MVB system which to process data’s transmission and the receive builds.
Actual profile
After composing the procedure, a recompilation QuartersII project document, will obtain .pof document downloading to FPGA, after on electricity, measures with the oscilloscope outputs the base pin, then may observe the MVB frame profile. Compares the IEC-61375 protocol standard, may judge this profile for the meet standards correct profile, and in the source port node has received the correct data, thus proves this process data port’s success refurbishing.
Conclusion
At present the domestic train network and the control technology are develop in the technology aquisition foundation, the overseas manufacturer is only willing to provide the product, but does not transfer the key technologies. Because purchases the network special-purpose chip alone with difficulty and so on all sorts of reasons, at present still uses the foreign product directly, or with overseas (design) the network card (ten thousand Yuan above high prices) and so on carry on the system integration, by this constitution train communication network (i.e. manufacture domestically). The present paper launches the research regarding the MVB main line first floor agreement, based on the SOPC design concept, to used FPGA to realize the IEC61375 agreement to carry on the attempt, has completed the MVB network I kind of board card design initially. At present, realizes the aspect to this network protocol also only to be restricted in the initial period stage, has only realized MVB main line basic process data receiving and dispatching. This system following must join the news surveillance data and so on correspondence. In actual node application, also possibly has various problems to need to perform to improve.
Reference:
1. IEC61375-1-1999, Part 1: “Train Communication Network”
2. zur Bonsen, The Multifunction Vehicle Bus (MVB), Factory Communication Systems, 1995
3. Jaime Jiménez, José L.Martin, Carlos Cuadrado, Jagoba Arias and Jesús Lázaro, “A Top-down Design for the Train Communication Network”, 2003 IEEE
4. Alberto Chavarría, Joseba López de Arroyabe, Aitzol Zuloaga, “Slave node architecture for train communications networks”, 2000 IEEE
5. The opening wave, the king construct, “MVB Main line Real-time Agreement Realizes And Experimental study”
6. Marquis Ningxia, Ding disabled soldier, Wang Yongxiang, Wang Lide, “MVB Network card’s Frame Transceiver Design”
