Abstract: KS8993 is American KENDIN Corporation develops contains 3 port 10/100 physics level transceiver the high performance quick ethernet exchange electric circuit. Introduced in detail DS8993 the major function, the characteristic and the main connection, have given KS8993 in the IP electric circuit’s application example.
Key word: KS8993; Medium irrelevant connection (MII); VLAN; Using
Chinese Library classification number: TN915.05 document code: B article serial number: 1006-6977 (2006) 01-0038-03
1 introduction < ?XML:NAMESPACE PREFIX = O />
KENDIN Corporation promotes KS8993 is the field first section contains 3 port 10/100 physics level transceiver, 3 to have 1 Layer2 converter’s MAC unit as well as the buffer high performance ethernet exchanges the electric circuit fast, integrated 10BaseT/100BaseTX/100BaseFXPHY and 16K×32 the SRAM buffer, its band width may achieve 1Gbps. Has the low power loss, the function complete and easy to debug and so on characteristics.
KS8993 mainly has the following characteristic:
Conforms to the IEEE 802.3 ethernet standards and the IEEE 802.3μ fast ethernet standard;
Support based on port’s VLAN, based on hardware’s 10/100 speed transformation and automatic consultative mechanism;
Supports 10M/100M and the full-duplex/half-duplex auto-adapted function;
Supports full-duplex’s IEEE802.3x flow control and the half-duplex flow control;
Internal integrated address comparison engine, automatic address analysis, aging and shifting;
MAC address from study, from renewal function;
May support priority lining up, the shielded twisted pair and the optical fiber;
Uses 128 pins the PQFP seals.
2 internal structures
Figure 1 is the KS8993 internal structure diagram. Following introduces in KS8993 each main module principle.
(1) address comparison engine
KS8993 built-in saves the MAC address and the related information address comparative table. This table can supply the 1K character 48 central address memory address and the exchange information.
(2)SRAM buffer
KS8993 built-in uses in saving the frame 16K the character 32 SRAM buffers. This resources are share by this electric circuit’s 3 ports. Each port assignment big space’s buffer may decide through the system establishment.
(3) flow control
In KS8993, the frame receive and the transmission support the 802.3x standard. KS8993 just received a data packet, if this data packet’s goal port resources are taken, KS8993 to will receive the data packet the port to carry on the flow control. By now, KS8993 will send out one to include the biggest stop time flow control frame. Once the goal port resources are released, KS8993 sends out other not to contain the stop time frame.
3 KS8993 input connections and output interface
As shown in Figure 2, the KS8993 input connection and the output interface mainly divide into: Physical interface, MII connection, serial network interface, LED instruction connection, non-management programming connection, control and other connections, factory test connection, power source and place connection.
3.1 physical interfaces
KS8993 provides 3 group receiving and dispatching signal connection separately, divides into the transformer and the optical fiber two kind of patterns and the media medium is connected. Under the optical fiber pattern, three group light signal examination connection meets the optical fiber signal detection outlet to be possible to complete the light signal examination. Must for the transmission data establishment tapped transformer reference value, and establishes the transmission magnitude of current.
3.2 medium irrelevant connections (MII)
Medium irrelevant connection (MII) the function is enables the physical level to be possible to support the different medium type. The MII pin signal including the receive, the transmission data, the transmission enables, the conflict monitor, to receive and dispatch the clock and the failure indication and so on. Also has provided the carrier activity, the collision detection and manages the connection signal. The data passes through MII the speed is each clock cycle is -and-a-half bytes (4), namely 25Mbps.
MII work in forward and under backward two kind of patterns. Under the forward pattern, KS8993 MAC3 carries on the correspondence using external connection PHY; Under the backward pattern, exterior MAC carries on the correspondence using KS8993 PHY3.
3.3 serial network interfaces
The serial network interface with uses in the network level protocol processing the controller being compatible, may direct and these type device attachment. The transmission signal divides into two kinds: A kind is responsible to transmit, enables, the collision detection, the serial transmission data and the transmission clock including the transmission and so on. Another kind is responsible to receive, including carrier monitor, serial receive and receive clock.
3.4 LED instruction connection
The status indicator signal may establish as the speed instruction, the conflict instruction, the full-duplex/half-duplex instruction and so on. May according to need external connection certain number the LED lamp indicating circuit’s working condition.
3.5 non-management programming connection
Establishes the MODESEL[3:0] pin level according to the function table to be possible to stipulate LED the working pattern. Establishes the MTXD[3:1] pin to be possible to realize the full-duplex and the half-duplex pattern. Establishes the MIIS[1:0] pin to cause KS8993 the MII connection work at forward or the reverse pattern. Establishes the MRXD[0] pin is the high level, KS8993 may forbid MAC3 the automatic consultative function. Establishes the MRXD[3] pin is the low level, causes KS8993 the MAC3 work in the half-duplex pattern. So forth, nimbly establishes these non-management programming connection level also to be possible to realize the automatic consultative mechanism, the MAC address from the study, to conform to functions and so on 802.1p priority lining up, from renewal.
3.6 controls and other connections
Meets the exterior crystal oscillator or the input clock signal and the system reset signal.
3.7 power sources and place connection
KS8993 uses the list 2.5V working voltage, including receives and dispatches driver’s total power loss is 300mA (750mW), has the low loss characteristic.
4 model applications
KS8993 contains 3 port 10/100 auto-adapted physics level transceiver and 3 has Layer 2 converter’s MAC units.
In the practical application, KS8993 already may dispose is an independent 3 port component, like Figure 3 (a) shows, may also to meet the needs (for example DSL is connected with a IP telephone and PC when), disposes into two ports to add a MII port’s form, like Figure 3 (b) shows. The MII port may connect the exterior processor, uses in the route goal and the public network visit.
Figure 4 is KS8993 in the IP telephone’s application. The port 1 connects the personal computer, the port 2 connects the telephone, the port 3 pieces establishes the MII port, uses in the route goal.
KS8993 each port is equipped with a 3 VLAN mask register (PV1, PV2 and PV3). Through the establishment register’s in mask, may establish in KS8993 3 port’s functions, a typical application is establishes 2 ports the switch, another port establishes as the router. Must realize this function, 3 VLAN mask register’s establishment is PV1 (1,0,1), PV2 (0,1,1) and PV3 (1,1,1). In this establishment, KS8993 may use in connecting 2 VLAN, VLAN1 including the port 1 and port 3, VLAN2 including the port 2 and the port 3. When VMDIS (Vlan Mismatch DIScard) =1, the port 1 and the port between 2 cannot the direct communication, this time the port 3 probably carries on the routing in port 1 respective VLAN1 and between port 2 respective VLAN2. When VMDIS=0, what if port receiving and dispatching broadcasts the data packet, then between all ports may the direct communication; What if port receiving and dispatching broadcasts the data packet, then these data packet’s transmission will be limited in identical VLAN. VMDIS=0 this characteristic often uses in broadcasting/broadcasts much the protocol conversion.
5 concluding remark
Uses when KS8993 must pay attention: Under the reverse operation, the MII connection does not provide to KS8993 meets reports the wrong signal, but under the forward pattern, does not provide sends delivers the paper the wrong signal; When necessity, when KS8993 cannot achieve the sending-end voltage value (approximately 2.2V or is higher than 2.2V), may the supply voltage enhance 2.65V; When wiring, the simulation and the digit should separate, is only connected in the power source place simple point, prevents to have the disturbance.
