Abstract: Introduced that one kind designs the microcomputer protective system control interface with VHDL on the CPLD chip the method to enhance the resistance to interference, the test result indicated: Control interface’s resistance to interference is very high, realizes the microcomputer protective system’s redundant reliable control completely. The connection speed is high, the high integration rate, can direct and the high speed DSP system connection, has the high promoted value.
Key word: Microcomputer protection; Antijamming; Redundancy design; VHDL; CPLD
Directing Word
The microcomputer protective device is refers to the microcomputer system constitution the digital relay protection installment. In our country coal mine shaft high pressure (6kV) power supply system, the overwhelming majority belongs to the transformer neutral point insulation movement way (three-phase three-wire system), adopts the power electric cable power transmission. The coal mine shaft environment is bad, the space is narrow, the power electric cable occupies moistly for a long time, pours water on, in the corrosion environment, radiates the condition to be bad, the insulating ability easy to drop, has the single-phase leakage or the single-phase earth fault frequently. This kind of breakdown causes the normal phase voltage to elevate, if not the prompt power failure, will cause the heterogeneity to short-circuit, the force power failure, and will make the electric power breakdown to further expand. The high pressure flameproof switch microcomputer protective device is installs in the high pressure flameproof switch, to the mine shaft electric cable and current collector’s single-phase leakage or the single-phase earth, the short circuit, the overflow, the insulation surveillance, breakdowns and so on undervoltage has carried on the synthesis protection one kind of equipment, can excise the breakdown return route fast, the forestall trouble expands, the notice attendants investigate the breakdown source to eliminate abreast in row promptly. Therefore, sets the very high reliable request to the high pressure flameproof switch microcomputer protective device: When the breakdown occurs can act fast; When not breakdown, cannot move by mistake. However, the high-voltage switch make-and-break perceptual load (mine shaft electric appliance equipment will mainly be electric motor and so on perceptual loads) the time, the switch contact pulls the arc to have the very strong electromagnetic interference and the surge disturbance, the order of severity may cause CPU the procedure to run flies. This kind of electromagnetic interference is the high pressure flameproof switch microcomputer protective system’s top-quality strong jamming source, mainly traces into the channel invasion microcomputer protective system through the power line and the exchange mutual inductor. The microcomputer protective system long lasting work in this kind of strong electromagnetic interference, the resistance to interference becomes one of weight microcomputer protective system’s important targets.
Enhances the microcomputer protective device the resistance to interference basic way is blocks the syntype disturbance the coupling channel, sharpens the sensitive return route’s antijamming ability, designs measures reasonably and so on earth draining return route. The electromagnetic compatibility (EMC) design is a complex systems engineering, from the hardware considered that the antijamming design is very essential, but wants from the hardware the interference elimination to be completely impossible. Must from the software consider that the digital filtering and so on, very difficult to achieve the acme of perfection. The domestic technical personnel in the monolithic integrated circuit system, microcomputer observation system’s aspects and so on antijamming technology have done many research works, publishes the massive antijamming technology paper, may divide into two broad headings. One kinds are from the hardware circuit barrage signal invasion channel, like the analog channel adds the predicting filter, the mains input to add the power source filter, the switch to enter with adds the light pair to isolate, pCB layout and wiring antijamming technology, earth technology and shield technology and so on; Another kind is the software antijamming measure, including digital filtering, instruction redundancy, software trap, software and hardware watch-dog and so on. The hardware measure antijamming is resists the unwanted signal in the wrong side of the door, is the electromagnetic compatibility design main attack direction. The software antijamming is in the hardware not yet expires under the premise, counter-balances the disturbance using software’s flexible design the influence, can only play the auxiliary antijamming role. Are very few about the microcomputer protective device’s control export reliability design’s literature, induces, prevents to control the export out of control commonly used measure to have two kinds: Hardware redundancy design and software redundancy design. The hardware redundancy design essential method uses pair or the multi-CPU structure, the start which is responsible to protect, another CPU is responsible for the execution which protects. Two CPU “and” only then starts to control the export. The software redundancy design mainly uses following measure:
(1) establishment multiple trip orders, are divided the control commands to carry out are divided the floodgate, carries out a section of checkup procedure between each instruction, establishes the corresponding flag bit. After CPU checks the flag bit match case, only then execution next instruction, otherwise the initialization comes again.
(2) establishment current output state register’s status messages, the systems operation self-check program circulation inquiry tests these conditions, if the discovery disturbance makes a mistake, corrects output channel’s error message promptly.
The multi-CPU structural design is prevents the protection to move by mistake, enhances the microcomputer protective system reliable one effective action, but uses the multi-CPU structure to make the hardware architecture to be complex, the debugging is tedious, the cost is high, moreover, when at the same time multi-CPU the procedure runs flies, similarly creates the control export out of control, has the possibility to cause moves by mistake. The software redundancy design is proposes (i.e. supposition CPU operating procedure in the program run normal condition to be correct, has not gone off track), if the procedure runs flies, already did not carry out the software redundancy project approach, then the control export is at the out of control condition, since the watch-dog electric circuit has an effect, causes CPU to reposition returns the normal procedure, the experience time is shortest also takes several milliseconds. During this period of time, the unwanted signal causes the control export to harm the trip sufficiently. Obviously, the above two methods cannot guarantee the relay protection control export completely the reliability and the security.
To the microcomputer protective system, a most important spot is when after the strong jamming causes the procedure runs flies, cannot cause the relay protection control export misoperation. The author in develops in the KJ118 mineral product transformer substation long-distance supervisory system necessary high pressure flameproof switch microcomputer protective system, in view of the relay protection control export’s characteristic, creatively proposed that uses the CPLD technology, strengthens the microcomputer protection control export the reliable research, the success designs one kind to export the hardware circuit based on the CPLD antijamming microcomputer protection control. In the article introduced this kind based on the CPLD control interface antijamming design’s new method, is simpler than the multi-CPU structure, is more economical, the reliability is higher, does not rely on CPU resistance to interference, even if the CPU procedure runs flies, the control interface still had the very high resistance to interference, will not produce trips by mistake the level, thorough settlement relay protection systems control export reliable question.
CPLD technology in microcomputer protective device application superiority
CPLD (complex programmable logic device, complex programmable logical component) with FPGA (field programmable gate array, the scene programmable gate array) is two big programmable ASIC (application specific intergrate dcircuit) the chip, available VHDL (very high speed intergrate dcircuit hardware description language) carries on the description and programming downloading. The CPLD gate array scale compares FPGA to be small, the CPLD primary structure is based on the product item, easy to realize the complex combinatory logic. The CPLD logical great unit compares FPGA to be few, the many trigger sequential logic uses FPGA to be appropriate. The FPGA primary structure is based on the SRAM table look-up item, although the circuit structure disposition is flexible, but the time delay cannot predict that the actual transmission time delay must be bigger than CPLD. CPLD uses the EEpROM programming technology, the power failure disposition information does not lose. FPGA uses the SRAM craft switch technology, on the electricity carry on the function disposition through online may the reshuffle way to FPGA, theoretically may the non-time limit disposition, and may realize in the true sense online may dispose, but the power failure disposition bit drop-out, must draw support from serial EEpROM, the monolithic integrated circuit and so on to carry in the electricity reshuffle. Regarding the I/O quantity and the trigger number not too big application situation, CPLD surpasses FPGA in the use conveniences and the programming secrecy.
In the microcomputer protective system’s digit combinatory logic electric circuit and the sequential logic electric circuit scale is not big, uses the CPLD chip to realize suitably, is advantageous to the microcomputer protective system’s microminiaturization and the intellectualized design.
Microcomputer protective device control interface design
The microcomputer protective system’s control interface is composed of the I/O connection and the miniature relay, the typical circuit is divides the closing relay to divide into 2 levels, the 1st cascade control 2nd level. The 2nd cascade control main return route’s minute switches on the contact device. Functional block diagram as shown in Figure 1.
2 levels of relays are advantageous in isolating the main return route’s minute to switch on the disturbance which the contact device make-and-break produces.
Switches on the instruction execute order is: OUT1→OUT2→OUT4. The minute floodgate instruction execute order is: OUT1→OUT3→OUT4. If the I/O connection controls directly by CPU, when CPU is disturbed the procedure to run flies or the CPU chip crashes causes the I/O connection out of control, when just in time has the level which the analysis and synthesis floodgate needs, the relay protection control export inevitably occurs moves by mistake. 
Figure 1 relay protection control export principle
Therefore, the relay protection control export’s block system and the redundance design are prevent to control the key which the slip in speech moves to be. The strict surveillance minute switches on the multiple orders the execution sequences, does not allow the disorderly minute to switch on the order to pass, is prevents to control the basic measure which the slip in speech moves. The minute switches on the multiple orders the order executions, may regard as a change of state sequence, carries on the monitoring with the CPLD state machine to this condition sequence, can cease the disordered state passing, realizes the control export non-interference control.
Based on CPLD state machine’s antijamming control interface design
When designs one based on the DSP high-pressured switch cabinet microcomputer synthesis protective system, realizes the I/O connection which with a piece of CPLD chip shown in Figure 1, and designs a limited state machine, inputs I1, I2, I3 to the condition to carry on the monitoring, the state machine outputs as the total score switches on the order the permission and the locking signal. Based on CPLD microcomputer protection control interface as shown in Figure 2.
Figure 2 the microcomputer protects CPLD control interface
The minute switches on the multiple orders the condition codes
The state machine has 3 binary inputs, altogether has 23=8 to plant the condition. Will use the binary system encoding method (Binary coded) control interface original state S0 to all possible condition vicissitude, the row to become one to arrange the stopwatch, as shown in Table 1. The condition arranges the stopwatch is compiles the VHDL procedure the foundation.
Table 1 microcomputer protection control interface state machine arranges the stopwatch 
State machine design
State machine’s clock rate is 5MHz. Reset signal /Reset from DSP microcomputer protective device system reset signal, to state machine’s condition initialization.
State machine’s design may use the single advancement, the double advancement, 3 advancements and so on carry on the compilation, uses the double advancement according to the microcomputer protection control interface’s application characteristic to describe the state machine suitably, namely a succession advancement and a combination advancement. The succession advancement is responsible for the old time condition to the new present condition transformation, as well as asynchronous replacement. The combination advancement completes acts according to the change which the present condition decision state machine outputs, decides the new time condition according to the condition input. Double advancement state machine’s functional block diagram as shown in Figure 3. 
Figure 3 pair of advancement state machine logical diagram
State machine’s behavior and the code are one kind of flow control codes, very easily sentence and the IF sentence realizes with VHDL in the language CASE. Between the succession advancement and the combination advancement uses the present condition signal and the time condition signal carries on the synchronous communication.
State machine simulation profile
To uses the VHDL language design using Altera Corporation’s EDA tool software MAX plus the state machine to carry on the succession simulation, simulation profile as shown in Figure 4. 
Figure 4 state machine simulation profile
CPLD state machine antijamming control principle analysis
Based on the CPU microcomputer system is according to the instruction cycle order execution machine instruction, once is disturbed the procedure to go off track, then CPU according to does not compose beforehand the flow executive routine, appears halts, the countermeasure usually is establishes the watch-dog to cause the CPU hardware to reposition, causes the CPU roll back normal procedure, but halts from CPU to the watch-dog replacement must experience several milliseconds generally to arrive at 1~2s, this period of dead times, the relay protection control export’s condition is uncertain, to the relay protection system constitution harm, the grave circumstance is sufficiently occurs moves by mistake. But based on the CPLD state machine system, the state transition cycle has a clock cycle, if the clock rate is 5MHz, the clock cycle is 012Ls. If the state machine is disturbed enters the illegal state to change over to again the legitimate condition, only needs 2 clock cycles, namely several hundred nanoseconds, are insufficient to the state machine systems operation to cause the harm. Obviously, with the CPLD state machine control microcomputer relay protection’s control interface, can realize the non-interference control, obtains the relay protection system’s redundant reliable control.
On the DSP chip and the CPLD chip’s reliability, the DSP periphery connection is comparatively speaking many, the input signal has the simulation and the digit, the voltage has the analogue voltage and the digital voltage, CPLD only then the digital interface, the voltage is unitary, the external interference damage’s possibility many which is smaller than DSP. Moreover, the CPLD state machine includes many advancements, quite in contains has the concurrent operation “multi-CPU” the function, to the unqualified input, adjudicates the state machine to output 0. Therefore, the author believed that the double CPU control hardware redundancy designs was inferior far the CPLD state machine’s control interface reliability is high.
Knot Theory
Realizes the relay protection control interface with Altera Corporation’s MAX7000 series EMp7128SLC84-15, with TMS320F240DSP chip main line direct connected, when the DSP execution switches on or the minute floodgate multiple orders, does not need to insert the waiting cycle, only needs to carry out 3 to switch on or the minute floodgate instruction continuously, the CPLD state machine can decide immediately whether to allow the total executive command to pass. The experiment indicated: The relay protection control interface which realizes with CPLD has the speed to be quick, takes the hardware volume to be small, the connection is simple, reliable higher characteristic.
This connection applies based on the TMS320F240 high-pressured switch cabinet digit synthesis protective device, threw along with the KJ118 mineral product transformer substation long-distance supervisory system in October, 2003 in the Xuzhou mining bureau Chishan coal mine shaft working area transformer substation transports, carries on the industrial experiment, the normal operation has surpassed above until now a half year. The working area transformer substation scene highly explosive switch artificial analysis and synthesis floodgate operation, the ground main engine guidance command divides switches on as well as the fail safe trip experiment indicated that because never has the high-voltage switch minute to switch on the operation and so on strong electromagnetic interference to cause the CPU procedure to go off track moves by mistake, displays the very high reliability.
In the article with the brand-new CPLD state machine method study microcomputer protective system’s control reliable question, has the very strong filter regarding the transient unwanted signal. Although goes off track from the guard microcomputer protective system procedure uses some software measure to have certain effect, but cannot solve the procedure offtracking period control mouth out of control problem truly, but in the article proposed the CPLD state machine control interface has solved this problem truly, may promote to each kind of microcomputer control system’s antijamming control interface design.
