The MCS-5l monolithic integrated circuit series belongs to 8 monolithic integrated circuits, it is Intel Corporation after the MCS-48 series success design, promoted the product in 1980. Because the MCS-51 series has the very strong internal function and the command system, thus caused monolithic integrated circuit’s application to have a leap, this series’s product also very quickly became in the world the second generation of standard controller. the 5l series monolithic integrated circuit has 5 interrupt sources, including 2 are the external input turban breaks source INTO and INTl. May ITl(TCON.2) and ITO(TCON.1) controls the external input by interrupt control register TCON to interrupt l and to interrupt 0 interrupt triggering way separately. If is O, then external input interrupt control for level triggering way; If is 1, then controls for the border triggering way. Here foot drops along the triggering interrupt.
1 question derivation
The nearly domestic all monolithic integrated circuit material to the monolithic integrated circuit border triggering interrupt’s response time aspect’s definition is not explicit or is wrong. For example in the literature is “(i.e. border triggering way) must examine two times about the border triggering interrupt response time’s description regarding the pulse triggering way the level, if the preceding time is the high level, the latter time is the low level. Then indicated that examined negative jump valid interrupt request signal”, but the actual situation was actually not true.
We knew that the monolithic integrated circuit external input’s interrupt triggering level is the TTL level. Regarding the TTL level, the TTL logical gate outputs the high level the permission scope is 2.4~5 V, its nominal value is 3.6 V; Outputs the low level the permission scope is O~O.7 V, its nominal value is 0.3 V, in 0.7 V and 2.4 V between right and wrong Gao Feidi middle level.
Like this. In the reality with, the supposition monolithic integrated circuit external interrupt pin INT0 input yilu drops from 5V to the 0V drop along the signal, the monolithic integrated circuit obtains 2.4 V high levels in some clock cycle sampling INT0 pin; But when the next clock cycle arrival carries on the sampling, because the actual external input interrupt trigger pip becomes the low level by the high level often to require certain time, therefore, examines by no means the true low level (is possibly smaller than 0.7V), but is between the low level and the high level some floodgate level, namely 0.7~2.4V some level. Regarding this kind of situation. Whether thus the monolithic integrated circuit still setting interrupt triggering symbol the initiation interrupt? About this point, the component material which the domestic major part teaching material as well as the monolithic integrated circuit producer provides has not given the accurate definition, but this kind of situation truly will bump into the practical application.
Operational amplifier chip AD708 which produces by American Analog Corporation is an example, its slewing rate (slew rate) is 0,3V/μs, in is composed of the AD708 chip in the comparator electric circuit, its output square-wave’s drop along from 2.4 V drops to 0.7 V, needs the time approximately is: (2.4 V-0.7 V) /0.3V · μs-1=4.67μs. Namely needs approximately 4.67μs the transition time, drops along only then truly by the high level drop is the low level, in the practical application electric circuit, this fall time often may reach 10μs above. Regarding the precise measurement system, the such long indefinite time is unacceptable, therefore, it is necessary to carry on the precise determination to the monolithic integrated circuit border interrupt trigger threshold.
2 test profile design and analysis
In order to determine the MCS-51 monolithic integrated circuit to drop along the triggering actual time, uses the model which Agilcnt Corporation produces is the 33250A 80MHz function/random profile sends Niu Qi (function/arbitrary waveform genera-tor), has the cycle which like chart l shows is the 20ms cyclical profile.
This profile through monolithic integrated circuit’s external interrupt 0 inputs, may determine the drop along the interrupt triggering actual time, below carries on the concrete study to this profile. Establishment as shown in Figure 2 rectangular coordinates.
Supposes shown in Figure 2 profile the cycle is T, the monolithic integrated circuit drops y=y in the voltage ‘ the time triggering interrupt, t1 ‘, t2 ‘, t3 ‘ respectively be the around cycle interrupt trigger threshold, then has:
The above profile by the monolithic integrated circuit external interrupt O input, the choice border triggering way, through the interrupt service measured that takes T1 or the T2 value, thus may extract the interrupt to have time level value y ‘, namely border triggering interrupt actual time.
When uses the monolithic integrated circuit carries on the survey to the interrupt time, uses two counters, supposes for way l (16 counting ways). And, the first counter uses in recording starts from the procedure to carry out to the first drop the time which experiences along the arrival, the second counter uses for the recording program to start to carry out the second drop the time which experiences along the arrival, cancels two counter’s counting values then may obtain two drops along between time-gap. May know by the front analysis, this time-gap possibly has two kind of situations: One kind is the T1 time, namely t1 ‘ and t2 ‘ between time-gap; Another kind is the T2 time, namely t2 ‘ and t3 ‘ between time-gap. And, the T1 T2=T, T1 time must be smaller than the T2 time. Obtains T1 or the T2 time through the survey, use type (4) then may obtain the drop along the triggering interrupt time actual level.
3 test flows and corresponding monolithic integrated circuit procedure
This monolithic integrated circuit’s interrupt service flow as shown in Figure 3.
The corresponding interrupt service is:
Because the program execution has certain time delay, after interrupt returns, but must carry on the adjustment to two counter values of exports. This experiment uses the H5l/L simulator which great Peking Syndicate produces for the monolithic integrated circuit measurement system, obtains the T1 value is 6.514 ms, may result in by type (4): y ‘ =O.729V, namely, when y ‘ approximately is 0.73 V, the monolithic integrated circuit drops along the triggering interrupt.
4 conclusions
This article through designs a simple profile, has carried on the accurate survey to monolithic integrated circuit’s border triggering interrupt response time, thus corrected the domestic monolithic integrated circuit study material in the border triggering interrupt time aspect define clearly, and the final outcome underwent the experimental verification.
