Abstract: Introduced (data shunt) designs based on Altera Corporation FPGA high speed DMUX. Through with the DMUX special-purpose component’s comparison, explained this kind realizes the way superiority.
Key word: Data shunt; Signal integrity; Modulus switch; Scene programmable gate array
l introduction
Along with the signal rate and the band width enhancement, the signal gathering speed also correspondingly unceasingly enhances. Now the modulus switch’s speed already achieved 1 GS/s. Even 2 GS/s. Rear end the high speed modulus switch output data stream speed for a hertz milliardfold bit, will increase the memory and the data processing component’s design difficulty, will therefore change down diverges into solves this question essential method.
2 reduction of speed divergence method
The reduction of speed divergence usually has two kinds to realize the plan: First, uses the DMUX special-purpose integrated device, another kind is realizes DMUX on FPGA.
Generally speaking, these two ways can realize the reduction of speed divergence well, and does not have division the fit and unfit quality in the performance. But considered from the overall system, the second way surpasses the first way relatively, the reason is as follows:
(1) as a result of the craft aspect’s limit, the DMUX special-purpose integrated device working pattern is quite unitary, and cannot change. Usually DMUX special-purpose integrated device like TS81102 (Atmel Corporation) may realize 1:8 pattern (to reduce to data rate original 1/8, and gives 8 groups outputs) or 1:4 pattern (reduces to speed original 1/4, and gives 4 groups outputs).
the (2)DMUX special-purpose integrated device outputs the data rate is lower, its output takes the data line are more, but must reduce the data line, its data rate correspondingly will enhance, regardless of therefore it will use what kind of working pattern, the PCB design difficulty will be very big.
the (3)DMUX special-purpose integrated device power loss big (must be higher than 5W equally), must make its normal work, the power source power supply and the radiation question will increase the designed cost and the design difficulty.
the (4)DMUX special-purpose integrated device belongs to the special chip, is not easy to purchase.
Therefore selects another way to replace the DMUX special-purpose integrated device appears very essential.
May realize the DMUX function based on Altera Corporation FPGA. Its biggest superiority lies in the storage module and the data processing module may simultaneously realize in FPGA, compared DMUX the special-purpose integrated device FPGA such design system, in the structure simplified many, but the signal integrity actually to a great extent had the enhancement.
Below take 1:8 working pattern as an example, carries on the comparison to two way’s design proposals.
Chart l shows uses the DMUX special-purpose integrated device’s design proposal. After the simulated signal undergoes the high speed ADC transformation, outputs the high speed 8 bit data and l clock Clkl, these signals after the DMUX divergence forms 8 groups 64 data and l clock Clk2 again (this clock reduces to original 1/8). Afterward FPGA comes sampling these 64 bit data with Clk2, processes these data again under control signal’s control.
Realizes DMUX after FPGA, may arrives DMUX and the FPGA conformity the same place, as shown in Figure 2.
Compares with Figure 1, Figure 2 has abbreviated between DMUX in the PCB design and the FPGA 64 bit data line and 1 clock line, but these data lines and the clock line will usually be higher than 100 MHz, therefore cannot create the signal complete to the PCB wiring any consideration week serious drop. In Figure 2, DMUX realizes directly in FPGA, this may enhance the design the success ratio, the key is to a great extent looked that FP-GA can receive ADC 8 high speed data and 1 high speed clock. But in fact FPGA truly may achieve, below each aspect which realizes to it separately performs to introduce.
3 key which realizes based on FPGA DMUX
3.1 component’s choices
Must realize DMUX, FPGA in FPGA to meet two requirements: First, many high speed difference receive port; Second, FastDPLL (fast digital phase-locked loop). Many FPGA can satisfy this request, like Xilinx Virtex4, Virtex Pro series, Altera Stratix series (Stratix GX, StratixⅡWith Stratix). They have the characteristic respectively in the application, below only take the Altera Stratix series as regularly explained that realizes the way.
3.2 pin dispositions
Must receive ADC the high speed data and the clock outputs, must dispose these signal pin to the high speed difference receive pin on. But is not all difference pin can take the high speed difference receive pin. The data receive pin general definition is DIFFIO_RX_P, DIF-FIO_RX_N, the clock receive pin general definition is CLK_DIF-FIO_RX__P, CLK_DIFFIO_RX_N.
Also has certain request in the pin establishment position, like Stratix the GX component only may in BANKl, on 2 difference pin realize; Stratix ⅡThe component only may in BANK3, on 4, 7, 8 difference pins realize; But the Stratix component may in BANKl, on 2, 5, 6 difference pins realize. If receives the ADC signal the pin is not the disposition on these pins, then cannot realize DMUX in FPGA to receive these high speed signals.
Regarding clock pin, must dispose on these BANK special-purpose clock pin. If has many such clock pins to be possible to supply the choice, then must choose these Cload (load capacitance) a smaller pin, this regarding enhances the data the receive speed to have the help very much.
3.3 software establishments
On 3.3.1 FPGA pieces impedance realization
The receive modulus switch outputs the high speed difference parting line needs generally the terminal impedance match, if these reflexless terminal resistance depends upon the piece external resistance to realize, will increase the PCB layout wiring the difficulty and reduces the receive the signal integrity. The FPGA difference receive port has on generally the difference lamination the impedance matching, as shown in Figure 3.
Impedance (RD) in 100 ω~170 OMEGA, its typical value is 135 OMEGA, approaches in the difference parting line difference impedance. Depends upon these piece on matched resistance, then does not need again the external connection resistance, and will achieve compared to an external connection resistance better effect.
The software aspect only need establish the terminal impedance is Differential.
3.3.2 FPGA high speed difference receive module realization
Is mainly through transfers the altlvds module on FPGA to receive the ADC output the high speed difference digital signal, as shown in Figure 4.
in the altlvds module the integration has Fast DPLL, may take 45° as first-level adjust the input clock precisely through it along with the data between relations, thus guaranteed that establishes and maintains the time can satisfy the request.
the altlvds module also carries on the pair using the input clock to the data-in along gathering, transforms it into the parallel multi-channel data.
Its data-in’s channel number and the by-pass compared to may also establish nimbly through the software. The establishment receive data channel number most are many are 44 channels (limited to the FPGA high speed difference receive pin number), most may establish the by-pass ratio is 1:10 pattern.
In addition, in this module may establish the receive the highest data rate is 840 Mb/s, receives the clock is 420 MHz high.
3.4 software simulations
In Quartus ⅡAfter carries on DMUX simulation result as shown in Figure 5, data-in (idata) is 800 MHz, input clock (in-clk) is 400 MHz. From the simulation profile may see that although outputs the data is not to very, but outputs clock (kaniclkp) may guarantee that can receive the data completely.
Data-in (idata) will change l 000 MHz, input clock (inclk) changes 500 MHz, its simulation result was still good.
3.5 PCB designs
Must enable FPGA to receive the modulus switch’s output signal well, first should guarantee that between them the wiring difference impedance satisfies the request. Moreover wants the close neighbor every time to the difference parting line, and approximate and so on is long.
In addition must the FPGA high speed difference receive pin disposition in the FPGA periphery, guarantee as far as possible the modulus switch and in the FPGA segment has not had the hole as far as possible.
The PCB plate’s choice is also very important, must guarantee as far as possible between them the wiring arranges in the most outer layer, and the wiring flag must choose the dielectric constant small material as far as possible.
For the module in internal phase-locked loop can the normal work, but should also separate the internal phase-locked loop electric power supply with the exterior digital power source. In Figure 6 showed one electric circuit connection mode, separated through the big inductance two kind of power sources, through the many electric capacity parallel filter, guaranteed the supplies interior phase-locked loop power source’s stability again.
4 concluding remark
After the actual test, substitutes the DMUX special-purpose integrated device using FPGA to receive the signal which the modulus switch outputs, its receive’s data rate already surpassed 1 Gb/s, is higher than 840 Mb/s maximum speeds which in the component material assigns, achieves the design requirements completely.
