Abstract: This article proposed one kind confirms the platform based on the FPGA communications system baseband the design proposal. This platform uses two piece of high performance 3,000,000 levels the FPGA components and the high speed modulus/d/a converter, provided a hardware for communications system’s baseband design to realize with the algorithm confirms the platform.
Key word: FPGA; Baseband design; Mold/number switch; Number/mold switch
1 introduction
In the correspondence domain wireless communication aspect, renews and the new standard issue unceasingly particularly along with the technology, the designer needs a high speed general hardware platform to realize and to confirm own communications system and the related algorithm. FPGA (the scene programmable gate array) takes one large-scale programmable logical component, the architecture and the logical unit is flexible, the integration rate high, the applicable scope is wide, and the design development cycle is short, the design production cost is low, the development kit advanced and may the real-time online examination, widely applies in the product prototype project and the product manufacturing.
(Digital signal processor) or GPP (general processor) compares with traditional DSP, FPGA displays the very strong performance in certain signal processing duty, has, construction and the algorithm nimble, parallel computing, assignment memory as well as dynamic disposition superiority and so on high turnover rate, therefore very suitable to use in designing the confirmation high-speed service system’s baseband processing part.
This article proposes one kind based on Xilinx Corporation Virtex-ⅡThe series 3,000,000 level FPGA component’s communications system baseband design confirms the platform, is suitable in the high-speed service system baseband prototype project and related algorithm realization, and has succeeded applies in based on the IEEE 802.1la OFDM baseband system design.
2 system platform composition and function
The communications system baseband design confirms the platform mainly to have the following constituent: Power unit, FPGA and peripheral circuit, clock and reset circuit as well as modulus and digital-analog conversion electric circuit. The platform overall diagram see Figure 1.
Various units module’s function is as follows:
Power unit: Gives FPGA and other electric circuit power supply responsibly.
FPGA and peripheral circuit: Mainly by two piece of 3,000,000 level’s FPGA component constitutions, after disposing the electric circuit uses in the start, completes to the FPGA automatic disposition. Other main peripheral circuit also has the memory (SRAM and SDRAM) and the serial port communication circuit.
Clock and reset circuit: Provides the system clock and the reset signal for FPGA.
Modulus and digital-analog conversion electric circuit: Is mainly 1 piece uses in the digital signal transforming the simulated signal ADC, as well as l piece the simulated signal will transform the digital signal DAC.
The overall system platform’s principle of work is: Two piece of FPGA designs the transmitter separately (in chart l FPGA_TX) and the receiver (in chart l FPGA_RX). After the test vector enters the transmitter, undergoes the baseband code and the modulation, transforms the baseband simulated signal through DAC. ADC and the accepting circuit receive electric cable transmits the signal, transforms it the digital signal, after receiver demodulation and decoding returns to original state for the primary data, and compares with the test vector, obtains performance indices and so on error rate.
3 function unit’s electric circuit realizes
3.1 FPGA and disposition electric circuits
VirtexⅡSeries FPGA is Xilinx Corporation promotes in view of the high performance programmable solution first section of platform level FPGA component. Virtex-ⅡThe series component uses the advanced O.15 μm/0.12 μmCMOS 8 metal mixing techniques design, the essence voltage is 1.5 V, may support many kinds of interface standards according to the input output reference voltage’s different design, the internal clock frequency may reach 420 MHz, was considered that is the high speed low consumption ideal design.
Virtex-ⅡSeries component characteristic:
(1) internal clock frequency may reach 420 MHz, the input output speed may reach as high as 840MHz.
in (2) inlays the 18×18 special hardware multiplying circuit and the carry logic chain (Look Ahead Carry) realizes the high performance arithmetic processing function in advance.
(3) high performance’s internal memory Select RAM, each block storage capacity is 18 KB. Most provides 3 MB the block memory resources as well as 1.5 MB distributional memory resources.
more than (4) reach 12 digital clock administration module (Digital Clock Manager, DCM) and 16 overall situation clock multiplexing buffers, has provided the nimble system clock solution.
(5)Virtex-ⅡUses the numerical control impedance matching technology (Digital Controlled Impedance, DCI), may reduce the system which creates because of the impedance matching question not to be unstable, and reduces the complexity which because PCB the reflexless terminal resistance causes.
This platform uses two piece of 3,000,000 Virtex-Ⅱ The FPGA component, the model is XC2V3000C, considered from the compatibility and the extension, selects the FFl152 seal, this seal and the XC2V4000/6000/8000 FPGA pin is compatible, is advantageous for the system upgrade.
Virtex-ⅡFPGA disposition information storage in SRAM, after the power failure, disposes the bit drop-out, after on electricity, needs to redeploy downloading. Virtex-ⅡThe series component disposition has 5 kind of patterns, JTAG/Botmdarv Scan, Master Scrial, Slave Serial, Master SelectMAP, Slave SelectMAP. And Master SelectMAP and MasterSerial need to use Xilinx special-purpose PROM.
This design uses JTAG/Boundary the Scan disposition pattern, mainly completes all disposition task through four special-purpose disposition holding wires. Provides two collocation methods; first, the online downloading disposition, through downloads the electric cable is connected the FPGA JTAG mouth and the computer and the mouth, uses the software to complete online downloading. Another kind uses the SystemACE plan, after on electricity, reads in the CF memory’s configuration files through the SystemACE controller, disposes the connected FPGA component through JTAG.
SystemACE the CompactFlash(CF) use based on the CFACompactFlash standard’s memory, is composed of the CompactFlash storage module and the ACE controller. The ACE controller has the built-in control logic, may through any ACE controller connection (the CompactFlash connection, the CFGJTAG connection, the TESTJTAG connection and system microprocessor connection) carries on the disposition to the goal FPGA chain. And the CompactFlash connection provides to the CompactFlash memory stick support. Monolithic Virtex-ⅡFPGA needs the layout data size is 300 Kbit-29.O Mbit, this means that uses Svs-temACE the CF plan to be possible to dispose surpasses 250 maximum capacity Virtex-ⅡSeries FPGA. The designer may according to need to change ACE Flash nimbly the density.
SystemACE disposition schematic drawing as shown in Figure 2. After completing the FP-GA design, designs the downloading configuration files through the software production, puts in through the CF card reader-writer the document in the CF memory stick. When in after platform electricity, the ACE controller reads in the CF card the configuration files, downloads through the JTAG chain the data to each FPGA, completes the automatic disposition. May also through JTAG downloading cable connection TEST the JTAG connection, carry on the online disposition directly to FPGA.
3.2 clock circuits and replacement and voltage monitor circuit
This platform uses two mutual independent active crystal oscillators to provide 20 MHz clocks, separately as receiver and transmitter’s clock source. Because on the board many place places need 20 MHz clocks (for example ADC and DAC), but only depends on the crystal oscillator supplies clock besides to cause the driving influence to be weak, will also possibly have the big clock displacement or the vibration. Selects clock driver IDT74FCT38074 is the system provides the clock, this is section of 3.3 V power supplies, the CMOS craft 1 drives 4 clock drivers, the input clock most to be high is 166 MHz, simultaneously provides 4 group low displacement synchronism clock. Through two piece of IDT74FCT38074, respectively provides the precise clock be the receiver and transmitter each module. After the input clock enters FPGA, may through the DCM frequency division frequency multiplication processing, be the clock which the FP-GA interior each functional module provides needs.
In Virtex-ⅡIn the component, all DCM module assigns through the clock multi-channel multiplexer logic to the component. Provides 16 overall situation clock buffer may realize 16 clock territory control, had guaranteed the DCM module’s clock outputs has smallest transmission delay (Skew).
The replacement and the voltage monitor circuit use MAX708SCPA, provides on the electricity automatic reset and the hand reset. MAX708SCPA PFI pin for surveillance voltage input end, when the PFI input voltage is lower than 1.25 V, the PFO pin outputs the low level expression voltage to be excessively low, in this design uses in monitoring the FPGA 1.5 V essence voltages. Switch button S8 provides the hand reset. Its electric circuit schematic drawing as shown in Figure 3.
3.3 digital-analogs and a/d conversion electric circuits
This platform uses in confirming the correspondence baseband system, needs I group which, Q group signal outputs the transmitter through d/a converter (DAC) to transform the simulated signal, the receiver through modulus switch (ADC) the received signal will transform the digital signal. This platform design uses ADC and DAC respectively are ADI Corporation’s AD9238 and AD9765.
AD9238 is double channel 12 ADC. The speed rank divides into 20MS/s, 40MS/s and 65MS/s. The power loss is 180mW~600mW, is suitable in requests the low power loss and the small PCB area application. AD9238 signal-to-noise ratio (SNR) is 70 dB, non-stray signal dynamirange (SFDR) is 85 dBc. Has the internal wide band difference sampling maintains amplifier (SHA), the permission user choice many kinds of input ranges and the offset voltage, including single end input. AD9765 is the twin port, the high speed, the double channel, 12 bit CMOS d/a converter (DAC). It integrated 2 high performance 12 bit TxDAC. The update rate may reach 125 MS/s, non-stray signal dynamirange (SFDR) is 75 dBc, O.1% gain displacement match rate. The output for the difference electric current, the full scope is 20mA.
In this design, the AD9238 work in the 2Vp-p difference working pattern, uses the materials for internal reference voltage, two channel work in sharing voltage reference pattern. The input difference scope is 2 V. The signal clock input may use the clock driver’s 20MHz output or provide by FPGA, the highest sampling rate is 40 MS/s. The AD9238 two port select AD8138 achievement transports puts the driver, is ADC provides the differential input signal. The AD9765 work in the twin port pattern, two channel gain control may adjust separately, uses the internal l.2 V reference voltage. The clock input may also use the clock driver’s 20 MHz output or provide by FPGA. AD9238 and AD9765 and the FPGA connection schematic drawing distinction like chart 4 and shown in Figure 5.
3.4 power circuits
This system normal work needs two kind of power line voltages. One kind is the FPGA component’s essence voltage 1.5 V; Another kind is the FPGA component’s input output interface voltage 3.3 V, this voltage simultaneously also uses in other component power supply.
This design uses suits the FPGA application the low voltage, the big electric current linear voltage regulator (LDO) power supply plan. The mains input uses the standard the ATX power source connection, may by the ATX power source power supply, 12 V inputs supply power directly to the ventilator, uses in the FPGA radiation. 5 V inputs through Tl Corporation’s TPS75533 and the TPS75415 distinction transformation are 3.3 V and the l.5 V voltage output. TPS75533 is a section of lowest differential pressure may be 250 mV LDO, may provide 3.3 V,5 a output. TPS75415 may provide 1.5 V,2 a output, its fast transient response may improve the system performance effectively. LDO uses the linear adjustment principle, the output ripple is very small, the peripheral circuit is simple, only requests the external connection input and the output capacity then works. The shortcoming is the voltage transfer efficiency is not high, the calorific capacity is big, requests to the radiation control aspect high. TPS75533 uses to-220 seal, may radiate effectively through the back radiator fin, but TPS75415 uses PowerPADTM the TSSOP small seal, in provides the 2W radiation power, enhanced radiation at the same time to save has taken the area.
Of 3.3 V and between 1.5 V voltages adds the protection circuit which the zener diode and the Short base diode constitutes, guaranteed that FPGA difference of the essence voltage and the connection voltage based on this, prevents the component damage.
4 OFDM baseband system confirms the platform design
Confirms the platform based on the FPGA communications system baseband design to be suitable for the high speed wireless communication system’s baseband design. Uses this platform to be possible to confirm based on the IEEE 802.1la OFDM baseband system’s simplification prototype project. Design diagram as shown in Figure 6.
After the confirmation, this platform can realize the OFDM prototype’s transmission and the receive function, and can confirm synchronized and the channel estimate algorithm actual performance effectively.
5 concluding remark
Confirms the platform based on the FPGA communications system baseband design to use large capacity, the high performance FPGA component, provided an effective hardware for communications system’s baseband design to realize the platform. Unifies based on FPGA realization with the confirmation and the computer simulation, will accelerate the communications system baseband part greatly the fast prototype project, has facilitated enormously has the high request each kind of algorithm confirmation to timeliness and the operand.
