Does wants: Discussed in detail in MAX plusⅡDevelops under the platform to use the VHDL hardware describes when language design scene programmable gate array (FP-GA) the common three questions: And so on dutyfactor frequency dividing circuits, time delay random quantity delay circuit, bilateral circuit.
Key word: FPGA; VHDL; Frequency dividing circuit; Delay circuit; Bilateral circuit
1 introduction
Along with the EDA technology’s development, uses the hardware language to design programmable logical component (PLD)/scene programmable gate array (FPGA) to become one tendency. FPGA is the new component which one kind of general’s family array’s general structure and the PLD scene programmable characteristic knot bes in one, has the integration rate to be high, the versatility is good, the design is flexible, the programming is convenient, the product goes on the market quickly and so on many merits. American Xilinx Corporation was in the lead in 1985 has promoted FPGA. At present in the market applies the widespread FPGA product, when counts Xilinx Corporation’s Spartan and the Virtex series and Al-tera Corporation’s ACEX and the APEX series.
At present the most main hardware description language is VHDL and Ver-ilog HDL. The VHDL development, the grammar is early strict, but VerilogHDL is the hardware description language which develops in the C language’s foundation, the grammar is free. In the project application in the related control circuit’s design, will meet the following three questions frequently particularly with VHDL hardware description language design FPGA: Realizes and so on dutyfactors, non-and so on dutyfactor integer frequency division frequency dividing circuits; Under clock controlling to synchropulse signal random time quantity detention; Uses the VHDL language to carry on bilateral circuit’s design.
2 frequently asked questions
2.1 frequency dividing circuits
The frequency dividing circuit is in the number system design basic electric circuit. In the hardware circuit design, the clock signal is one of most important signals, needs to carry on the frequency division operation frequently to the high frequency clock, obtains compares the low frequency the clock signal. The frequency dividing circuit divides into three kinds generally:
The first kind is the random dutyfactor even number frequency division and non-and so on dutyfactor odd number frequency divisions, usually completes by the counter or the counter cascade.
The second kind is and so on dutyfactor odd number frequency dividing circuits. Must realize the dutyfactor is 50% M=2N 1 frequency dividing circuit, this article uses the counter and 1 or gate realizes.
Using clock’s rise along the counting, designs mold M the counter: Drop along when judges the counter the value and has the dutyfactor is 1:2N M frequency divider C1; Rise along when judges the counter the value and has the dutyfactor is N:N 1 M frequency divider CO. Two frequency divider’s outputs look carefully or already may realize and so on dutyfactor M frequency dividers. The procedure attaches. Figure 1 is and so on dutyfactor 5 frequency dividing circuit’s simulation profiles.
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If joins the judgment sentence finally in the above procedure, then this section of procedures may realize and so on dutyfactor random frequency divisions, judges M-N the odevity: M-N is the even number, CO is the frequency division output which wants; M-N is an odd number. C0 C1 is the frequency division output which wants.
The third kind is the decimal frequency dividing circuit. Realizes the frequency division coefficient is the N-0.5 frequency divider. May use 1 mold N the subtraction counter, 1 different or gate, 1 2 frequency dividers. Must want to use the identical electric circuit to complete the many kinds of form half frequency divisions, may add 1 in the half-integer frequency divider principle foundation to the different or gate to enable the control signal.
2.2 delay circuits
The delay circuit is in the electronic design the commonly used electric circuit. When studies the digital circuit uses 555 integrated timers to realize the pulse detention, but when clear signal processing, many designs cannot use 555 integrate the timer to complete. With VHDL language design when generally realizes with the counter or the counter cascade. Below by an example explained how to realize the random time quantity time delay.
Control carries on the N time delay in 5 MHz under the clock CLK to synchronized signal SYNC (the SYNC pulse width is 2 μs, the pulse rate is 1 kHz; 0μs≤N≤998 μs). Request each time when synchropulse rise along arrival starts the time delay, and after the time delay had ended has the width is 10 μs gating signals.
Needs to produce time delay succession as shown in Figure 2 (time delay quantity N=4.2μs).
Here uses 3 counters and 1 or gate produces the above time delay signal, as shown in Figure 3, the mold N counter counts the time delay quantity; The mold 50 counters count the gating signal the width; The mold N 50 counter uses in producing enables the signal. Carries on with the VHDL hardware description language when the hardware circuit designs, in the identical advancement cannot use 2 clocks to trigger, but in the succession chart requests in the synchropulse SYNC rise along to start the time delay, to solve this problem, has used the mold N 50 counter and 1 or gate.
When synchropulse for high level, the mold N counter and the mold N 50 counter starts to count, juxtaposes dly_en is the high level. The mold N counter is full, sets at dly_enl is the high level simultaneously produces the gating signal. When the mold N 50 counter counts the full being appointed to fill a vacancy correspondence number to produce postpositioned dly_en is the low level. Immediately when a synchropulse arrival above is redundant the process. This kind of designa circuit’s advantage is when synchropulse width change and does not have the influence to the sequential control, because has only used the SYNC rise in the counting process along, started from the time delay to the gating signal to finish, under the or gate function SYNC to the counter not control action.
The above electric circuit’s VHDL procedure is as follows:
This program selection N=20, namely the time delay quantity is 4.2 μs, because must use the clock to judge SYNC the rise along the situation, therefore, if N=0, is produced the delay signal will still have 1 clock’s inherent time delay, when calculated the time delay quantity should consider this point fully, the time delay quantity = (N 1)× clock cycle. This procedure is a radar target simulator sequential control procedure part, it produces the time delay uses in the dummy target the distance, along with the goal movement, the request simulation’s time delay quantity must change, each time synchropulse rise before arrival, Accountant DSP figures out the time delay to measure N and to give FPGA through the data bus.
2.3 bilateral circuits
In the project application, the bilateral circuit is the question which the designer must face.
When uses VHDL language design FPGA, will meet many interface control electric circuit frequently the design, for example FPGA and external storage unit’s interface circuit design, FPGA and DSP interface circuit’s design, FPGA and CPU interface circuit’s design and so on, data bus’s design will be inevitable, but the data bus will often be bidirectional. Therefore, how processes the data bus is correctly carries on the sequential logic circuit design the foundation.
In programming process, bidirectional signal both as signal input and as signal output. The common bidirectional signal’s pattern has two kinds, the first kind is the bidirectional signal takes a signal the input, takes another signal the output; The second kind is the bidirectional signal both and makes the input as the output. Uses frequently the data bus is the second kind of pattern. Must carry on bilateral circuit’s design well, the key lies in the entity part to carry on the explanation to the port attribute, the port attribute must be the inout type; Is constructing in vivo to need to carry on to the output signal has the condition high-resistance control.
Following unifies section of procedures to explain compiles when the data bus with VHDL should pay attention question, first kind of pattern bidirectional signal compilation and this similar.
DBus is the data bus, datal6 (15 downto 0) and SA (18downto 0) is 16 and 19 registers, dlyL and dlyH is datal6 enables the end, AddrLReg, AddrMReg, AddrHReg is SA enables the end.
dlyL or dlyH are when the high levels FPGA reads the data from the data bus (time delay quantity), locks in existence data register datal6; AddrLReg, AddrMReg, AddrHReg have 1 for the high level when FPGA delivers the condition register SA value on the data bus.
In the bilateral circuit programming, the DBus input is the ordinary in type, but when output needs to add certain control requirement to control the high-resistance condition. Last cannot omit, it explained the bidirectional signal’s three states of matter output, needs to pay attention to behind when the sentence condition limit, if the condition limit will be too wide wrongly will take the bidirectional signal main line, will cause main line’s misoperation; If the condition limit is too narrow, output register or’s data cannot deliver the data bus correctly, causes the data loss. Generally may use the address wire which the enumeration law 11 uses to display, will express only will then only then use the data bus in such address wire situation, otherwise other conditions will enter to the data bus high-resistance, expressed that will not take the data bus.
3 concluding remark
The DSP technology has the widespread use in many domains, formerly frequently used fixed function’s DSP or ASIC may provide the very good real-time performance, but its flexibility is bad, does not suit in situation uses and so on laboratory or technology development; DSP receives certain limit in the software algorithm, therefore uses DSP and the FPGA union is carries on the digital signal processing one tendency, but uses VHDL/VerilogHDL hardware description language design CPLD/FPGA is also a technology which the electronic designers should grasp.
