Abstract: Has designed based on FPGA and with the MCS-51 monolithic integrated circuit instruction compatible highly effective microprocessor essence. This essence improved the traditional MCS-51 monolithic integrated circuit’s architecture, causes each machine cycle only to need a clock cycle, enhanced the instruction to carry out the efficiency. Simultaneously increased the hardware watch-dog and the software reset function, enhanced system’s reliability and antijamming ability. This essence adopted the function simulation and downloads to FPGA in succeeds the movement.
Key word: FPGA microprocessor essence watch-dog MCS-51
Throws the piece with the tradition to realize ASIC to compare [1], FPGA to have realizes the speed to be quick, the risk small, programmable, may momentarily change the promotion and so on a series of merits, thus obtained more and more widespread application. The MCS-51 application time is long, the scope is broad, related software and hardware fruitful in resources, thus often inserts the MCS-51 essence in the FPGA application to take the micro controller. But the traditional MCS-51 instruction efficiency is too low, each machine cycle reaches as high as 12 clock cycle [2], must therefore improve to the essence, raises the instruction execute speed and the efficiency, can satisfy FPGA well the application.
Through for the traditional MCS-51 monolithic integrated circuit instruction succession and architecture’s analysis, used the VHDL language to use a design method redesign highly effective micro controller essence from the top. Improved the architecture, may compatible MCS-51 all instructions, each machine cycle only need 1 clock cycle, simultaneously increased the hardware watch-dog and the software reset function, raised the instruction execute efficiency and antijamming ability.
1 system design
1.1 module divisions
This essence when divides and the design module, based on the following several principles:
(1) synchronized design, enhances the system stability and the probability; (2) function is clear, the function close places in the identical module to reduce the module between quantity and the module interconnection line, simultaneously favors when the synthesis optimization; between (3) module’s connection succession defines in advance, and compiles each module strictly according to the definition succession request; (4) module signal’s output selects the method which the register outputs. This may enhance system’s reliability, once makes a mistake easily also to determine that the question is.
This essence is composed of following several parts: Central control unit (CPU), arithmetic logic arithmetical unit (ALU), register group controller (REGS_CTR), the timer/counter (T/C), the general serial interface (UART), the watch-dog (WT_DOG), as shown in Figure 1.
1.2 raise the speed the method
This essence uses following several means to raise the speed.
(1) uses the multi-data channel: This essence has cancelled the traditional MCS-51 series monolithic integrated circuit’s unified bus, uses the straight company structure, the various modules’ data transmission use unidirectional special-purpose data line, especially uses four unidirectional data line interconnections between data exchange frequent ALU and REGS_CTR, enhanced the data transmission degree of parallelism, thus sped up the data transmission.
(2) uses the double-phase clock: As shown in Figure 2. The CLK clock rises along CPU sends out the control signal, the I/O port sampling external signal is Figure 1 the average enters REGS_CTR the data or the control signal; The CLK1 clock rises after reads in the data in the register and sends out the refurbishing data or the control signal, namely Figure 1 empty arrow expressed the data flows. Such REGS_CTR read-write in two clock’s rises along, reduced a clock cycle waiting separately, the clock rate enhanced one time.
(3) uses the register group: The FPGA interior has the quite rich the register resources, this essence cancelled the RAM block which the traditional same time only could read or write, the generation by has been possible simultaneously to carry on the different address read-write operation the register group. Some special function register has the special-purpose bus out, as shown in Figure 3.
(4) raises the clock rate: Has made the transformation to electric circuit’s critical path, reduces the logic circuit progression, thus raises the clock rate. Through these designs, had guaranteed each machine cycle only needs a clock cycle, raised the instruction execute efficiency, simultaneously also raises system’s clock rate.
1.3 compatible aspect considerations
The MCS-51 series monolithic integrated circuit has the rich software and hardware resources, to use these resources fully, when this essence design considered as far as possible strengthens its compatibility. Besides the machine cycle becomes original 1/12 as well as increases a special function register (address F8H) to use in newly controlling the watch-dog and the software repositions, other do not have the change. Therefore when single essence application, the beforehand procedure may transplant completely; When with outside correspondence, because the machine cycle and the MCS-51 monolithic integrated circuit has the difference possibly to make the corresponding modification to some procedures. This may make the system while to enhance the performance not to need other expenses, is advantageous for the promoted use.
2 functional module design
2.1 central controllers (CPU) design
This is the micro controller’s core, is responsible for the interrupt processing and the instruction execute. The interrupt processing divides into the interrupt sample, the interrupt height priority judgment and the execution corresponding treating processes. CPU divides into four stages to the instruction execution: Takes refers to - the decoding, the execution, the execution - to return writes, returns writes - prefetching to refer. Instruction execute flow as shown in Figure 4.
In the code realizes in the way, this module is a big fathers and sons two level of state machine, the father state machine for the instruction type, sub-state machine for each kind of instruction execution step. Such structure is clear, favors the programming, Zha Cuoji the simulation.
2.2 register groups (REGS_CTR) design
This module completes under the CPU control: Address on the program production, height 128 register’s read-write. The program counter with produces the corresponding instruction address according to the control signal from the register group’s data and escorts to ROM. In the register group’s read-write, with reads the decoding circuit choice output operation data, writes the decoding circuit to read in the result data. This kind of structure may while writes to a register reads another register. As shown in Figure 3, the general data bus may obtain any register’s data, each special-purpose register also has the respective special-purpose data line output. When for example executive order ADD A, DIRECT, because accumulator ACC has the special main line, so long as gives correspondingly reads the control signal to be possible to obtain from the conventional data main line from the register group’s DIRECT data, such ALU may obtain two operands which in the identical cycle needs.
2.3 watch-dog (WT_DOG) design
The traditional MCS-51 series monolithic integrated circuit to enhance outside the antijamming ability usual use to set at the watch-dog or to use the software trap the way to cause the system reset. This essence increased the hardware watch-dog and the software reset function, through increases a special function register (address F8H) to control newly whether to begin using the watch-dog or the software replacement as well as the establishment watch-dog feeds the dog time. Only if power failure or with the procedure reset, the F8H register’s value has preserved, after like this has avoided the watch-dog replacement, its own expiration question.
2.4 arithmetic logic arithmetical unit (ALU) design
The accumulator sends out in CPU under the command control, to comes from ROM and the REGS_CTR data completes the corresponding operation, including arithmetic operation (arithmetic operations) and logic operation (and or non-) and BCD code adjustment. All operation’s result obtains in a clock cycle, in the clk1 rise after arrival reads in REGS_CTR.
2.5 serial modules and fixed time/counter design
The serial module and fixed time/the counter working pattern and the traditional MCS-51 series monolithic integrated circuit is the same. Fixed time/a counter clock cycle counts one time, counts an effect with a traditional MCS-51 monolithic integrated circuit machine cycle to equate. When corresponds with the outside with the serial port the machine cycle has the difference.
3 simulations, the synthesis optimize and realize
3.1 simulations
In order to guarantee that the essence works correctly, must make the full simulation to the electric circuit to guarantee the design the accuracy. After the system design completes, has carried on the function simulation with ModelSim Se PLUS 6.0D to the electric circuit, (for example ALU) used the exhaustion test vector method to the combinatory logic module to give the function simulation, regarding succession module like CPU, whether tested the correct execution-interruption and each instruction first, then tested the stochastic instruction and the stochastic interrupt. The simulation result indicated that the essence can satisfy the design the request. ALU simulation result as shown in Figure 5.
And rom_data, acc, regs_data are the ALU operands, instruction is the instruction category, alu_rslta, alu_rsltb is the ALU operating result high, the low byte. As seen in Figure 5, in the input operand and carrying overflow in the position flag bit invariable situation, the different instruction can output the correct result which corresponds. The ALU operating result’s data locks saves, until when next instruction or data arrival only then changes. At maintains in the instruction invariable situation changes the data-in and carrying overflows the position flag bit also to be able to obtain the correct result.
3.2 synthesis optimizations
To raise the clock rate as far as possible, must reduce the critical path the time delay. Because ALU all operations must complete in one cycle, thus operates the longest time which needs is also the clock cycle minimum value. After generalized analysis, discovered that what the operating time is longest is the division operation, uses the ordinary shifting cancellation divider to need the time is 39ns, if after using the parallel divider, only needs 23ns, thus obviously raised the clock rate. After essence synthesis, consumes LUT is 4500.
3.3 realize
This essence’s entire job completes under the ISE7.1 development environment. And, what simulation with is ModelSim Se PLUS 6.0D, the software which the synthesis uses is Synplify Pro 8.0. The confirmation uses the platform is CREAT-SOPC1000X experimental box [3], what its core chip is the FPGA use is Xilinx Corporation’s Virtex-Ⅱ xc2v1000 -6 fg456, equivalent is 1,000,000 gates, as shown in Figure 6. In the platform integrated some commonly used functional module, in which crystal oscillator is 50MHz, after having surpassed this essence synthesis upper frequency, thus designed a 5 frequency division module to cause the clock is 10MHz. The essence movement’s test order and the data “the solidification” substitute ROM beforehand by machine code’s form in a program module, the system may look like ROM equally to its read data and the procedure. P0-3 output observed data, test routine whether to carry out correctly. The confirmation result indicated that the essence can carry out the procedure which and the steady operation correctly loads in the 10MHz frequency.
In order to overcome the traditional MCS-51 monolithic integrated circuit to carry out the efficiency somewhat low shortcoming, satisfies present’s FPGA to the embedded soft nuclear speed high request, a redesign compatible MCS-51 instruction embedded soft nucleus. This soft nuclear instruction efficiency enhanced 12 times, simultaneously increased the practical function: The hardware watch-dog and the software reposition. The essence has certain application value through the FPGA confirmation.
Reference
[1] Han Jungang. Struggle of by ASIC and the FPGA. Computer project, 2004,30(8):10-11.
[2] Yang Zhonghuang and so on. Single chip 8051 practices and application. The first edition. Beijing: Chinese Water conservation Water and electricity Publishing house, 2001.
[3] CREATE-SOPC 1000X experiment instruction book. www.hncreate.com.
