Abstract ADS8344 is 8 channels which TI Corporation produces, 16 lives, the high accuracy, the low power loss A/D transformation chip. This article introduced the ADS8344 main feature, and gives take its and FPGA as the foundation data acquisition system, as well as hardware circuit and corresponding hardware description language design method.
Key word ADS8344 front end FPGA data acquisition
The data acquisition in the industry test system is a very important link, its accuracy and the reliability are very important. This article elaborated the data acquisition system precision reaches as high as 16, can carry on a/D sampling to 8 exterior analog channels, the biggest simulator input scope achieves - 15~ 15V. This system has the restriction protection function, the programming is simple, can realize to far-end data gathering and the transmission.
1 system hardware design
Data acquisition system diagram as shown in Figure 1.
In the chart, a/D switch used TI Corporation’s 16 to approach ADS8344 gradually; FPGA mainly uses in controlling ADC the start, to stop and to inquire the ADC condition and so on, simultaneously carries on the high speed data cushion, the asynchronous data to the data to arrange the decoding, the wireless channel to arrange data processing and so on decoding.
1.1 main chip ADS8344
ADS8344 is a section of high performance, low power loss ADC, uses the 2.7~5V single power source power supply, the biggest sampling frequency is 100 kHz, the signal-to-noise ratio reaches 84dB, the bringing sampling/maintains an electric circuit, contains 8 single end analog input channel (CH0~CH7), may also synthesize is 4 differential inputs. The reference voltage VRFF scope is 500mV~VCC, the corresponding each analog channel’s input is 0V~VREF, DS8344 is corresponds mutually through three SPI connections and FPGA, the data inputs from the DIN pin to 8 only writes controls the register. When FPGA reads the ADC previous transformation result, next transformed channel’s control byte to write about the DIN pin. A complete control byte needs 8 DCLK clocks. Finished the control byte at the same time, the mold/number transformation finishes, mold/number transition status output pin BUSY had a drop along, the data output was effective, FPGA started to receive the transformation result which output by DCUT. 16 serial bit data need 16 DCLK clocks, when receive serial data LSB position, the next channel’s control start of word inputs to a/D chip. ADS8344 completes a time complete data sampling maintains, the transformation and the output altogether needs 25 DCLK clocks. ADS8344 serial interface succession as shown in Figure 2.
1.2 signal recuperation electric circuit
Front end data acquisition’s recuperation electric circuit as shown in Figure 3. what 2 transport puts selects is TI Corporation’s precision instrument amplifier OPA277. Because the input analogue voltage signal is a bipolarity, the scope is 115 ~ 5 V, but the ADX8344 analog input channel is O V~VREF (this system is 5 V), must therefore carry on the unipolarity transformation to the input signal.
Its transfer function is:
In the formula: After VOUT is the transformation unipolarity voltage signal; VREF provides by the voltage datum source, in the chart is 2.5V; VIN is the input 115 ~ 15 V voltage signal. When R3=6R1, R4=6R2, the transfer function may simplify is:
Obviously, the transfer function is the linear function. So long as chooses the precise resistance value correctly, 115 ~ 15 V voltage signals may the linear transformation be O~ 5V, thus has guaranteed system’s precision.
1.3 wireless channels
This system is according to user’s request design development, the wireless channel is provides by the user. This system uses the wireless channel is the point-to-point transmission, the transmitting range is farthest reaches 40 km, the transmission speed is highest reaches 11 Mbps, to the standard asynchronous serial port data is the transparent transmission. A/D electric circuit outputs data after FPGA data processing and so on high speed data cushion, asynchronous data coding, wireless channel code, delivers the wireless channel to carry on the wireless transmission. After the far-end wireless receiver receives the data, delivers FPGA to carry on processing and so on wireless channel decoding, asynchronous data decoding, restores a/D sampled data, then or delivers the D/A electric circuit to carry on the simulation quantity output, or carries on the asynchronous data coding to deliver PC machine, makes the further analysis processing by PC machine to the data.
2 software designs
This system’s software design has included the FPGA hardware description language programming and the PC machine application procedure.
2.1 FPGA programming
The FPGA programming uses the VHDL language, mainly includes to the ADS8344 data read-write, the asynchronous data arranges the decoding and so on. Uses FPGA to be very easy to realize correspondence between the SPI connection, only uses two advancements to the ADS8344 data read-write to be possible to realize. The subprograms are as follows:
(1) writes the data advancement
In the procedure 8 control byte is requests in another advancement according to the user to carry on the disposition. The control register form is as follows:
Controls the register everybody’s function explanation to be as follows:
The S– control byte starts the position. When for high, only then expressed that the input byte is effective.
A2~AO– analog input port select position.
SGL/DIF– analog channel input mode choice position. When for high, is when the single end inputs i for low, is the double-end differential input.
PDl~DO– power management choice position.
(2) reads the data advancement
ADS8344 is the multichannel A/D transformation chip, therefore the data must increase the channel address. After FPGA has read 16 bit data, carries on high speed data cushion processing, the service speed and the low speed asynchronous serial port speed matches. Because reads the data is 16, but the asynchronous data is 10 (1 outset position, 8 bit data positions, l stop position), must therefore code to the data. Realizes the asynchronous data format with FPGA to be simple. Below is the asynchronous data coding subprograms:
In the data coding advancement, pdatam (15 downto 0) is 16 bit data which A/D transforms, divides into 4 asynchronous data frames. Each frame’s low 4 are the data positions, high 4 are arranges the symbol, data coding form like table l arranges in order.
After superior PC machine assigns the speed receives like the table l form 4 asynchronous data frame, removes the outset position, the stop position, the address position and the idle position, arranges the data according to the address position order, obtains the D15~D0 16 A/D quantized data, PC machine may make further processing to the data.
2.2 PC machine programming
The PC machine end’s application procedure is environment develops in NI under Corporation’s LahView, mainly uses to the data which gathers carries on the solution seal, demonstrated that the control entire data acquisition system carries on, the stop, establishes some corresponding parameters, as well as carries on final data analysis processing.
3 conclusions
This systems synthesis has utilized the FPGA hardware description language change circuit structure, the algorithm technology and the wireless point-to-point transmission technology, unifies the application both in long range data gathering. This system user contact surface is friendly, the operation is simple, the precision, the speed as well as the system reliability satisfy completely request. This system applies in some research institute experiments data acquisition transmission between the airship and the ground. The practice indicated that this system suitable to use in requests the gathering channel to be many, the precision is high, but in speed request not high data acquisition.
