The abstract convolution code is one performance fine error control coding. This article elaborated the convolution code codec encoder-decoder’s key job principle, in the MAX PLUS2 software platform, gave the use complex programmable logic component design (2,1,6) to convolute the code codec encoder-decoder electric circuit, and has carried on the translation and the profile simulation. After the synthesis, downloads to complex programmable logical component EPM7128SLC84-15, the test result indicated that has achieved the anticipated design requirements.
Key word convolution code; Encoder; Decoder; Complex programmable logical component
When the digital communication system carries on the data transmission, as a result of noise jamming’s influence, will have the mistake inevitably in the receiving end. For issues certain error rate target in the known signal-to-noise ratio’s situation, in the reasonable design baseband signal, the choice modulation, the demodulation way, and uses the balanced measure in the foundation, but should also use channel coding technologies and so on error control coding to cut the error rate. The grouping code and the convolution code are the error control coding two main forms, in the encoder complex degree same situation, the convolution code’s performance surpasses the grouping code, therefore, in such as GSM, IS95 and CDMA2000 and so on the wireless communication standard, has applied the convolution code.
CPLD is the complex programmable logical component’s abbreviation, it is the high density programmable logic component which the early-1990s appeared, used the E2CMOS craft manufacture, generally was composed of three kind of programmable electric circuits, then programmed the logical great unit, programmable input/output unit and programmable internal segment. It may use in EDA technology MAX PLUS2 to take the development kit, will design the circuit diagram or hardware description language compilation’s program synthesis Cheng Wang table file write in which, makes the ASIC chip. The CPLD prominent merit is may program repeatedly, the integration rate is high, the data rate is quick, simultaneously has the big flexibility.
1st, convolution code encoder
The convolution code (calls recurrent code), is one kind of non-grouping code which (P.Elis) proposed by Elias. It forms k bit information section n bit code group, not only this yard group with current k bit information section related, moreover also (N-1) the information section has the connection with front (N is bigger than 1 integer). Usually, records the convolution code does (n, k, N), k is the input element number, n is the output element number, N is the constraint length, indicates encoder’s memory progression. The convolution code belongs to the channel coding, mainly uses for to correct the element the random error, it is by sacrifices the efficiency to receive in exchange for the reliability, the use increases the surveillance position, carries on the error detection and the error correction.
The convolution code encoder is one by k input end, n out-port, and has the limited condition memory system which (N-1) the festival shift register constitutes, usually is called the sequential network. The convolution code’s encoding method has three operational modes: Separate convolution law, production matrix technique and multinomial product law. In addition, the convolution code’s code process may also use the state diagram, the code tree chart and the grid chart describes. This article designs encoder schematic diagram as shown in Figure 1, it for (2,1,6) convolutes the code encoder (in chart T is shift register).
Figure 1 convolution code encoder schematic diagram
May know by Figure 1, this encoder is one (2,1,6) convolutes the encoder, namely k=1 (an input end), n=2 (two out-ports), N=6 (5 level of shift registers).
If the infed information sequence is: U= (u0 u1 u2…), then the corresponding output is two symbol sequences:
C1= (c0 (1) c1 (1) c2 (1)…) C2= (c0 (2) c1 (2) c2 (2)…)
Its corresponding code equation may write is: C1 = U * G (1) C2 = U * G (2)
In the formula “*” the expression convolution operation, G (1) and G (2) expresses encoder’s two impulse response. The code output may obtains by infed information sequence U and encoder’s two pulse impulse response convolution, thus is called the convolution code. Because the encoder has 5 levels of registers, therefore the impulse response at most sustainably to 6, shown in Figure 1 the convolution code encoder’s two impulse response to be possible to write:
G (1) = (100000) G (2) = (100111)
If the infed information sequence is: U=(11010101), then:
C1=(11010101)*(100000)=(1101010100000)
C2=(11010101)*(100111)=(1100010001011)
Transforms after and the string, final output’s symbol is: C=(11110010001100100001000101)
2nd, convolution code decoder
The convolution code’s decoding may divide into the algebraic decoding and the probabilistic decoding two kinds. The large number logic decoder is the algebraic decoding most main decoding method, it then uses in correcting the random error, may also use in correcting the burst error, but the request convolution code is from the orthogonal code or may the orthogonal code, regarding (2,1,6) convolute code large number logic decoder schematic diagram as shown in Figure 2.
Figure 2 (2,1,6) convolutes the code large number logic decoder schematic diagram
In Figure 2, the input digital sequence,/and transforms after the string is two groups, 1 group produce information element, 2 group output verification element. The decoder 1 group each section of units of information which receives sends in the encoder to extract local verifies the Yuan, with verification Yuan mold 2 Canada which its behind receives. If both are consistent, then extracts follows the type component is 0, otherwise is 1. Adds the value sends in follows in the type register to check. After receiving the code section, starts to the 0th yard section error correction, if this time large number logical gate’s output is 1, then explained that the 0th yard section the unit of information has the mistake. By now was just right the 0th sub-group the unit of information to move to decoder’s out-port, thus corrects them. At the same time, the correction signal also feeds back to follows the type register to revise follows the type, eliminates this mistake to follows-like the influence. If the large number decision gate has not output, then explained that the 0th sub-group the unit of information does not have the mistake, by now from encoder directly unit of information output.
3rd, realizes the convolution code codec encoder-decoder using CPLD
3.1 realize using CPLD (2,1,6) convolutes the code encoder
(2,1,6) convolutes code encoder electric circuit as shown in Figure based on the CPLD design 3.
Figure 3 (2,1,6) convolutes the code encoder electric circuit based on the CPLD design
Shown in Figure 3 convolutes encoder’s pin relations are: The pin DATA expression data feeds, pin CLK1 expressed that “and the string transforms” the input clock, the pin CLK expression data clock input pin (it may obtain by the CLK1 two frequency divisions), the pin DATA1 expression convolution arranges
The code output code C1 data, the pin DATA2 expression convolution encoder outputs code C2 the data. The pin DATAOUT expression convolution encoder passes through and the string transforms, final output code C data.
5 level of shift registers transfer a string from the MAX PLUS2 component storehouse to enter combine the shift register 74164 to realize; 4 levels of molds 2 add from the MAX PLUS2 component storehouse transfers 4 level of different or gates “XOR4″ the composition; “21mux” realizes 2 and the string transformation; After encoder’s two output code and the string transforms after output code, increased a D trigger respectively “DFF”, its function is uses the D trigger’s input end to the burr signal insensitive characteristic, the burr which on the destination CPLD component output pin possibly produces.
3.2 (2,1,6) convolute the code decoder using the CPLD design
(2,1,6) convolutes code large number logic decoder as shown in Figure based on the CPLD design 4.
Figure 4 (2,1,6) convolutes the code large number logic decoder based on the CPLD design
(2,1,6) convolutes the code large number logic decoder by 2 strings of bit/and the switching circuit, the surveillance code produces the electric circuit, the school positron computer circuit and the large number logic circuit is composed.
2 strings of bit/and transform “chuanbing12″ are transfer 4 D triggers from the MAX PLUS2 component storehouse “DFF”, as soon as 2 complementers design a two frequency dividing circuit and input two output strings/and the switching circuit and carry on the part packing warehousing to form, clock CLK obtains by the CLK1 two frequency divisions.
The surveillance code produces the electric circuit is transfers a string from the MAX PLUS2 component storehouse to enter combines the shift register 74164, 4 level of different or gates “XOR4″ the composition.
The school positron computer circuit is transfers 5 D triggers from the MAX PLUS2 component storehouse “DFF”, 4 different or gates “XOR” design component circuits.
The large number logic circuit is transfers 4 NAND gates from the MAX PLUS2 component storehouse “NAND3″, 1 NAND gate “NAND4″ and 1 different or gate “XOR” design component circuits.
3.3 (2,1,6) convolute the code codec encoder-decoder using the CPLD design
Will design (2,1,6) convolutes the code encoder to carry on the part packing warehousing will be “juan216″, will design (2,1,6) convolutes the code decoder to carry on the part packing warehousing will be “decode216″, afterward them connects in together, may compose (2,1,6) convolutes code codec encoder-decoder as shown in Figure 5.
Figure 5 (2,1,6) convolutes the code codec encoder-decoder
(2,1,6) convolutes the code codec encoder-decoder’s pin relations are: The pin DATA expression data feeds, the pin CLK expression input clock (its speed is data rate two times), the pin CLRN expression reset end, the pin CD expression (2,1,6) convolutes the code encoder to output, the pin OUT expression (2,1,6) convolutes the code decoder to output.
4th, experimental result
Carries on the translation and the simulation using the MAX PLUS2 development kit, (2,1,6) convolutes code codec encoder-decoder simulation profile as shown in Figure 5.
Figure 5 (2,1,6) convolutes the code codec encoder-decoder simulation profile
And “DATA” is the data input end, if system input’s data bit is “11010101″, after convoluting the code encoder, after time delay approximately 150ns, “CD” the output data bit is “11110010001100100001000101″; Passes through the convolution code decoder again, after the time delay approximately 1us, “OUT” restores the output data bit is “11010101″. The simulation result indicated: The encoder output data are completely consistent with the theoretical calculation. After will then synthesize, produces the net table document through the ByteBlaste downloading electric cable, downloads by the online disposition’s way to CPLD in component EPM7128SLC84-15, thus has completed component’s programming. After on electricity, joins in the input end treats the coded message, outputs with the digital storage oscilloscope test encoder, the actual result entirely accurate, has achieved the design requirements.
5 conclusions
This article elaborated the convolution code codec encoder-decoder’s principle of work, uses the CPLD component, designed (2,1,6) has convoluted the code codec encoder-decoder. This article author innovated to use in EDA technical MAX PLUS2 to take the development kit, will design the circuit diagram synthesized Cheng Wang table file write in which, made the ASIC chip, the prominent merit was may program repeatedly, the integration rate was high, the data rate was quick, from the top designed, search and revision wrong convenient, simultaneously first simulation, after correct, downloaded again tests and applies, thus had the big flexibility; Design mentality which proposed according to this article, may facilitate the design other convolution code codec encoder-decoder, has the broad application prospect.
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