Compares with the present broadcast, the digital audio frequency broadcast (Digital Audio Broadcasting, was called DAB) this kind of new transmission system to rely on its many merits to bring to the international correspondence profession attention, and has obtained the rapid development. Our country broadcasts the movie television profession standard “30~3000MHz Ground Digit Audio frequency Broadcast system Technology standard” implements from June 1, 2006. This standard is the DAB standard, is suitable transmits the high grade digital audio frequency program and the data traffic in the migration and the fixed receiver.
Because the handset television will be 2008 Beijing Olympic Games provides the service, the domestic many units have devoted positively to the DAB development. This article will introduce the DAB receiver’s prototypical design.
System’s performance requirement
The European DAB system had stipulated 4 kind of patterns, what this design uses is the 1st kind of pattern, concrete parameter as shown in Table 1. And, L expressed that a sign digit, K expressed each mark’s sub-carrier integer, TF expressed duration, TNULL expressed the spatial mark duration, Ts expressed each mark’s duration, Tu expresses the effective mark duration, DELTA expression protection gap duration.
Table 1 1st kind of DAB mode of transmission concrete parameter
Uses this pattern the design requirements is: Band width 1.536MHz, carrier frequency 174~240MHz, the error rate does not surpass 10-4.
Plan principle and design mentality
1 plan functional block diagram
DAB receiver functional block diagram as shown in Figure 1. The DAB receiver will receive from the antenna to the signal will transfer the intermediate frequency simulated signal after the high frequency tuner, after the enlargement, will carry on a/D transformation, will obtain the digital signal. And a/D sampling clock the crystal oscillator VCXO control, the sampling clock displacement is estimated by the sampling clock sync section obtains. After A/D transforms a data group makes the AGC examination to control high frequency tuner’s output, another one goes via R/C to transform two group solid imaginary component data signal which FFT needs. The time synchronism part estimated that obtains a time domain mark same pier, and estimated sketchily causes the frequency offset not identically as a result of the receiving and dispatching frequency. After the FFT transformation, the frequency synchronism unit decides on FFT the window position, the adjustment has the frequency offset data. After the adjustment data estimated after the channel that obtains the current real-time channel response, eliminates the influence which after the channel equalization treatment the channel multi-diameters decline, then maps the soft decision decoding reconciliation after the solution to harass again, then sends in the tonic train signaling the channel decoder decoding, then carries on the source decoding and the audio frequency is comprehensive, finally passes through the D/A reduction simulation audio frequency?
Figure 1 receiver functional block diagram
2 plan design mentalities
The DAB receiver mainly by the digit under the frequency conversion, the synchronization, the OFDM demodulation and Viterbi decodes four major part constitutions.
Under the digit the frequency conversion is becomes the ADC output intermediate frequency digital signal the digital baseband signal, is also realizes the frequency spectrum under removal in the digit, mainly includes Hilbert to transform, under the frequency spectrum the removal and falls the sampling and so on.
The sync section according to the function including the mark fixed time synchronization, the carrier frequency synchronization and the sampling clock rate synchronization, as may divide into the time domain synchronization and the frequency range synchronization two parts take FFT.
The OFDM demodulation including FFT and the difference demodulation and so on, interweaves after the frequency range solution carries on the QPSK solution mapping and the quantification again after FFT and the difference demodulation’s data, gives the following Viterbi decoder to carry on the soft decision decoding.
The data takeoff fast information channel which sends to the OFDM demodulation (FIC) the data carries on the solution contraction, the Viterbi decoding, the solution to harass, obtains the composite construction information (MCI), (MSC) the data carries on the decoding again using MCI to the main traffic channels traffic channel.
DAB receiver hardware circuit design
1 program structure diagram
According to the DAB receiver constituent’s analysis, this design uses FPGA DSP the design proposal, DAB receiver complete structure diagram as shown in Figure 2. DAB signal after antenna receive enters the high frequency tuner part, selects frequency block which needs, will then select the high frequency signal sends in the mixer, becomes the center frequency is 38.912MHz, the band width is 1.536 MHz intermediate frequency signals, after the intermediate frequency signal filters out the useless frequency spectrum part, passes through the frequency transformation and the filter again, becomes the center frequency is 2.048 MHz, the band width is the 1.536MHz baseband signal. Then enters ADC, the sampling speed is 8.192MHz, after transforming the digital signal, enters FPGA. FPGA completes and the string transforms, the synchronization and the demodulation, as well as VCXO needs control circuit and so on. After the processing data enters the DSP, DSP external clock is 24.5MHz, therefore DSP may carry on 4 frequency multiplications, works in 100MHz. In DSP completes the solution to interweave, the Viterbi decoding, Xie Rao as well as the audio frequency decoding, finally the data is sent in DAC, restores the primitive simulated signal, sends in the loudspeaker then to listen.
Figure 2 receiver’s structure diagram
2 component’s shapings
Component’s shaping request in satisfies the system requirements in the situation to argue vigorously causes the cost to be lowest, the power loss is smallest, and the design convenience easy to debug, must therefore give dual attention to the chip comprehensively the operating speed, the price, the hardware source, the operation precision, the power loss as well as the chip seal form, the quality specification, the goods supply situation and the life cycle and so on. The overall evaluation above several aspect factor, in this design ADC selects TLV5535, DAC to select AKM4352, FPGA to select EP1S40, DSP to select TMS320VC5510.
TLV5535 is section of performance fine 8 ADC, has the 35MSPS sampling speed, the 3.3V single power source power supply, the typical power loss only then 90mW, the analog input band width reaches 600MHz, very suitable this design. AKM4352 is very suitable portable audio equipment’s DAC, band width 20kHz, sampling speed 8~50kHz, the working voltage is 1.8~3.6V, the pass band fluctuation only then ±0.06dB, the stop-band weaken reaches 43dB, the performance is fine. TMS320VC5510 is a TI Corporation’s section of high performance, low power loss DSP. It has the very high code to carry out the efficiency, its highest instruction execute speed may reach 800MIPS, the double MAC structure, may establish the instruction cache memory capacity is 24KB, on the piece RAM altogether 160K×16b, in addition also has 3 group of multichannel cushion serial port and the programmable digital phase-locked loop generator and so on, the I/O voltage 3.3V, essence voltage 1.6V. EP1S40 is ALTERA Corporation Stratix series FPGA, has the very high essence performance, memory property, the construction efficiency, provided the special-purpose function to use in the clock management and the digital signal processing application and the difference and the single end I/O standard, in addition also had the internal match and remote system promotion ability, the function is rich, and the power loss was small. The EP1S40 internal resources also sufficiently satisfy this design to need.
3 main module circuit designs
ADC and FPGA are connected, and completes and the string transformation in FPGA, the decoding circuit also completes by FPGA. FPGA and the ADC connection including the data line and the clock line, the ADC clock provides by FPGA, data line and clock line with FPGA I/O pin direct connected then, as shown in Figure 3.
Figure 3 ADC and FPGA connection schematic diagram
DSP through the asynchronous serial port and the DAC connection, as shown in Figure 4, DAC output simulated signal after the filter may the direct output voice signal.
Figure 4 DSP and DAC connection schematic diagram
Nowadays’s high speed DSP memory no longer based on Flash, but uses access speed quicker RAM. After DSP power failure, in its internal RAM procedure and the data will lose completely, therefore in is separated from simulator’s environment, on after DSP chip each time electricity, must from lift, carries out the code the exterior memory block through some way removal to the internal memory block, and automatic execution. Commonly used from lifts the way to have parallel from lifts, serial from lifts, the host interface (HPI) from to lift from lifts with I/O. HPI from lifts needs to have a main engine to carry on the intervention, although may carry on the monitoring through this main engine to the DSP interior work situation, but the electric circuit is complex, the cost is high; Serial from lifts the code load speed to be slow; I/O from lifts only takes a port address, the code load speed is quick, but the electric circuit is complex, the cost is high; Parallel from lifts the load speed to be quick, although needs to take the DSP data area the partial addresses, but does not need to increase other connection chip, the electric circuit is simple. Therefore obtained the widespread application in TI Corporation’s 5000 series DSP, this design is also uses parallel from lifts. Compares with traditional EEPROM, Flash has the support online to scratch writes and scratches writes the number of times to be many, the speed is quick, the power loss is low, the capacity is big and merits and so on low in price. At present uses the 3.3V single power source power supply in many Flash chips, with the DSP connection when does not need to use the level switch chip, therefore the electric circuit connection is simple. When system programming, use system’s DSP to the external Flash programming, has saved programmer’s expense and the development time directly, causes DSP to carry out the code to be possible the online renewal. Figure 5 is the exterior program data memory Flash electric circuit connection.
Figure 5 exterior program data memory Flash electric circuit connection
FPGA and DSP through McBSP, GPIO, EMIF and the EHPI mouth are connected, the connection type are many, is advantageous according to needs to use nimbly. After FPGA procedure and data power failure, also completely will lose, thought its equipment special-purpose disposition chip EPC16, after on electricity, will download automatically the procedure to FPGA, simple easy to use.
Summary
For the convenience debugging, this design is very flexible, the system resources which remains are also quite many, not only may realize the pattern 1, other three kind of patterns may also realize in this hardware platform. Uses for the stored routine and data Flash already may use FPGA to come the read-write, may also use DSP to come the read-write. DSP and FPGA matched the JTAG downloading mouth to use in separately downloading the procedure and the examination chip. DSP also connects RS232, uses in issuing the control command as well as monitoring the DSP interior situation. After the FIC decoding completes, may carry on DAB/DMB the service choice, carries on different processing differently after the choice service has the sound and the image signal separately, and separately outputs from the loudspeaker or the liquid-crystal display.
