Abstract: In based on DSP system design, to guarantee when power failure the procedure does not lose, always procedure preservation in nonvolatile storage, so that system on electricity replacement time may guide it to DSP internal RAM to carry out. Take TI Corporation’s TMS320C6713 floating point DSP and AMD Corporation’s AM29LV040Flash memory as an example, designs one through the JTAG load completely from to lift the guidance plan. Described the guidance pin as well as the related register’s establishment emphatically, analyzed has used the EDMA transmission mode to duplicate the code from Flash to the DSP process, and gave to the vectoring procedure based on the assembly language code realizes. The project practice proved that this design proposal is feasible, effective.
Key word: TMS320C6713; From lifts the guidance; Flash
Introduction
In many based on the DSP system design, the procedure code always preserve in ROM, Flash or other non-volatile memory, guaranteed when power failure the code still existed, must therefore probably solve the guidance loading problem. When lifts guides (Bootload) is refers to the system the electricity, DSP section of memories in the exterior nonvolatile storage’s code removal to the internal high speed memory unit in carries out (for example internal RAM). This article take TI Corporation’s TMS320C6713 (below Jian Chengwei C6713) floating point DSP and AMD Corporation’s AM29LV040Flash memory as an example, designs a complete guidance loading plan through the JTAG mouth load.
TMS320C6713 guidance disposition
External signal BOOTMODE[4:3] had decided the C6713 guidance disposition, is gained in the RESET signal’s rise along the BOOTMODE[4:3] signal. C6713DSP has 2 guidance ways:
(1)ROM/Flash guidance. An exterior memory’s part passes the EDMA controller copy to DSP dummy home address 0. Although vectoring procedure in component after external reset release only then starts to carry out, but in CPU maintains when the internal replacement, this copy carries on. Flash width also through the BOOTMODE[4:3] choice. In the Flash width is smaller than in the 32bit situation, when DSP through the EMIF read, may automatic the neighboring 8bit byte or the 16bit half character pack forms 32bit the instruction word, and these values may through establish HD8 in the exterior memory to determine the endian storage pattern.
(2) main engine guidance. Core CPU pauses in the reset state, component other parts maintains the normal state. Exterior main engine through HPI or expansion main line initialization CPU storage space. After the essential initialization completes, the main engine controls register’s DSPINT position in HPI to write 1, this writes the operation to cause the DSPINT signal jump, thus causes the guidance disposition logic to cause CPU to be separated from the reset state, then CPU starts from address 0 to move.
Flash guidance pattern realization
Hardware design
The C6713 guidance pin explained that like Table 1 arranges in order.
When design pulls the resistance earth in DSP main engine mouth pin HD[4:3] HD4 through, HD3 pulls the resistance through on to meet the 3.3V power source, namely HD[4:3]=01B. C6713 EMIF includes 4 CE space register, because the Flash loading sequence is moves into from the CE1 space, therefore DSP CE1 with Flash(AM29LV040) selects patches or strips of land as worth saving for seed
connected, this kind of connection maps the Flash dummy home address DSP 0×90000000 place, thus has completed the basic hardware design. DSP and Flash connection’s hardware connection as shown in Figure 1.
Figure 1 DSP and Flash pin connection
Vectoring procedure design
Flash memory’s cleaning
In carries on the read-write operation before AM29LV040Flash, deals with it to carry on the cleaning, the cleaning operation needs 6 bus cycles:
(1) approaches 555H the address memory cell write data AAH;
(2) approaches 2AAH the address memory cell write data 55H;
(3) approaches 555H the address memory cell write data 80H;
(4) approaches 555H the address memory cell write data AAH;
(5) approaches 2AAH the address memory cell write data 55H;
(6) approaches 555H the address memory cell write data 10H;
After completing the above operation, the Flash memory cleans completely.
Under the CCS environment, compiles the above operation with the C language to be as follows:
voidFlash_Erase()
{
* (char*)FLASH_ADR1=0xAA;
* (char*)FLASH_ADR2=0×55;
* (char*)FLASH_ADR1=0×80;
* (char*)FLASH_ADR1=0xAA;
* (char*)FLASH_ADR2=0×55;
* (char*)FLASH_ADR1=0×10;
}
According to the front design, the Flash dummy home address already mapped C6713 the CE1 space, it starts the address is 0×90000000. Therefore the FLASH_ADR1, FLASH_ADR2 definition is as follows:
#define FLASH_ADR1 0×90000555
#define FLASH_ADR2 0×900002AA
Assembly source code file
Speaking of C6713, on after DSP electricity replacement, EDMA data (guidance code should locate automatically from CE1 the spatial copy 1KB with this) to address 0, then starts from 0 addresses place to carry out the guidance code instruction. This guidance code’s major function is duplicates the user segment from Flash to DSP in internal RAM, then skips again to the procedure entrance starts to carry out the master routine. Duplicates the segment in the vectoring procedure to use EDMA, by fast, realizes in nimbly the DSP storage space the data removal. The data removal’s source/goal may be the internal memory, the internal peripheral device or the exterior component. But this time needs to the EDMA source, the destination address, the removal length as well as the basic transmission mode carries on the related establishment, as shown in Table 2, then joins using the assembly language programming to the vectoring procedure then.
The core vectoring procedure is as follows:
.sect “.BootCode” ; The guidance code will assign to BootCode Duan Zhong
.global myBootCode
.ref_c_int00 ; C procedure entry point address
MVKL . S1EDMA0_OPT , A5
MVKL . S10×50010001, B4 ; Low 16bit reads in the register
MVKH . S1EDMA0_OPT , A5
MVKH . S10×50010001 , B4 ; High 16bit reads in the register
STW . D1B4,*A5 ; Loads EDMA the OPT parameter
MVKL . S1EDMA0_SRA , A5
MVKL . S10×90001000 , B4 ; Low 16bit reads in the register
MVKH . S1EDMA0_SRA , A5
MVKH . S10×90001000 , B4 ; High 16bit reads in the register
STW.D1B4,*A5 ; Loads EDMA the SRC parameter
….
….
Then starts the EDMA duplication master routine section: CPU may through write event setting register (ESR) to start a EDMA channel. In ESR some writes 1:00, will trigger corresponding forcefully the event. The procedure is as follows:
MVKL . S10×00000001, B4
MVKL . S1EDMA_ESR, A5 ; Low 16bit reads in the register
MVKH . S1EDMA_ESR, A5
MVKH . S10×00000001, B4 ; High 16bit reads in the register
STW . D1 B4, *A5 ; The ESR first position 1
NOP5
After end of transmission, skips to C procedure entry point address _c_int00 place, starts to carry out the master routine:
MVKL . S2_c_int00, B0
MVKH . S2_c_int00, B0
B.S2B0
NOP5
Link command file
The link command file is in the DSP performance history the production may the execution document (.out) an essential link. It has 2 to the section function; first, COFF which produces by the assembler the form OBJ document will take the input block, when has many documents carry on the link, the corresponding section will unify together is producing may carry out the output module; Second, locates, will output the section assigns to the memory in assigns the address.
When compilation command file, sometimes hoped that loads a memory’s place the code, but in another place movement. For example: Some keys carry out the code to install in system’s ROM, but hoped that moves in quick RAM. The link provided to deal with this issue the straightforward procedure. May let the link localization 2 times using the SECTIONS pseudo-instruction option. The first use loading key words load establishment load address, uses movement key words run to establish its movement address again. The loading address determined the section the primary data or the code load place, but any refers to its movement address to the section quotation. Must duplicate in the application this section from the loading address to the movement address, this vectoring procedure then uses the EDMA way to complete this copy process. Link command file (boot.cmd) as follows:
MEMORY
{
VEC:ORG=0×00000000, LEN=0×00001000
PMEM:ORG=0×00001000, LEN=0×00004000
CEVEC:ORG=0×90000000, LEN=0×00001000
CEPMEM:ORG=0×90001000, LEN=0×00004000
}
The above establishment is divides into the entire memory has the different name memory region. VEC, PMEM represents internal RAM two storage space, but CEVEC, CEPMEM represents in Flash two storage space. Each section’s load address and the movement address realize to the object file in the SECTIONS section.
SECTIONS
{
.BootCode:load=CEVEC; User’s guidance code section locates in the Flash most start.
.text:load=CEPMEM,run=PMEM; User segment loading in
Flash space, but moves in C6713 in internal RAM.
}
Online fever writes through JTAG the mouth Flash
Compiles a removal procedure with the assembly language, the content is only the Flash cleaning process, as well as operates the constitution to EDMA Flash to read in the process many times from internal RAM to the piece outside. This removal procedure direct inserting master routine, such procedure word length is very short, will not take the excessively many master routine spaces. Under main engine guidance way, after JTAG mouth load, the handwork changes the PC value to cause it to aim at this section of codes, controlled its movement to finish, completes from lifts the procedure the online fever to write. But after this, this section of short removal procedure any section of codes will not be transferred by the master routine.
Concluding remark
The project practical application indicated that this method is practical and feasible, compared with formerly the Flash vectoring procedure compilation method has avoided the target code format conversion, uses the EDMA direct removal, does not need the programmer, Flash does not need the frequent disassemblage, favors in the project the fast development.
