1NAND FlaSh and NOR Flash
Dodges saves (Flash Memory), because it has the non-volatility, the electricity to be possible, to be possible to duplicate programs as well as high density, low power loss characteristics and so on cleaning, widely is applied in data storage equipment and so on handset, MP3, digital camera, notebook. NAND Flash and NOR Flash are in the present market two kind of main non-easy accidents to save the chip. Compares with NOR Flash, NAND Flash in aspect and so on capacity, power loss, service life superiority causes it to become the high data storage density the ideal solution. The NOR Flash transmission efficiency is very high, but reads in with the erasing speed is low; But NAND Flash by the capacity big, writes the speed to be quick, the chip area is small, the unit density is high, the erasing speed is quick, the cost low status characteristic, appears the strong market competitiveness in the non-volatility class storage device.
Structure: NOR Flash is parallel, NAND Flash is serial.
Main line: NOR Flash is the separation address wire and the data line, but NANDFlash is the multiplying.
Size: Typical NAND the Flash size is NOR the Flash size 1/8.
Bad block: In the NAND component’s bad block is the random distribution, needs to carry on the initialization scanning to the medium to discover the bad block, and bad block mark for not available.
Position exchange: In NAND Flash occurs the number of times must be more than NOR Flash, suggested when uses NAND to dodge saves, simultaneously uses the EDC/ECC algorithm.
Application method: NOR Flash is may carry out (XIP, eXecute In Place) in the chip, the application procedure may in FIash dodges in directly saves moves, does not need to read again the code in system RAM; But NAND Flash needs the I/O connection, therefore uses time needs to read in the driver.
Through the above analysis and the comparison, NAND Flash suits in the large capacity data storage embedded system. This design selects NAND Flash which Samsung Corporation produces memory chip K9F1208 to take the storage medium, and using in based on uPSD3234A enlargement mode 8051 monolithic integrated circuit’s embedded systems.
2 uPSD3234A synopses
uPSD3234A is one section which produces by the Italian Law Semiconductor Company based on 8052 essence enlargement mode Flash monolithic integrated circuits, its structure as shown in Figure 1. This monolithic integrated circuit contains 1 belt 8032 micro controller’s Flash PSD, 2 Flash memory, SRAM, general I/O mouth programmable logic, the management monitoring function, and may realize USB, I2C, ADC, DAC and the PWM function. And, the internal 8032 micro controllers, have 2 standards asynchronous to pass unguardedly, 3 16 fixed time/counters, 1 external interrupt as well as JTAG the ISP connection (use in system programming), generally applies in grasps domains and so on equipment, domestic electric appliances.
3 K9F1208 introductions
K9F1208 is 512 Mb which Samsung Corporation produces (64M×8 position) NAND the Flash memory. This memory’s working voltage is 2.7~3.6 V, the internal memory structure is 528 byte ×32 page ×4 096, the page size is 528 bytes, the block size for (16 KB 512 bytes); May realize the procedure to scratch automatically writes, the page procedure, the block cleaning, the intelligence to read/writes with the cleaning operation, a time may read/writes or cleans 4 page or the block content, the interior has the order register. As shown in Figure 2, this component may divide according to the function is: The memory array, the input/output cushion, orders the register, the address decoding register and the control logic production. And, orders the register to use for to determine that the external instrumentation carries on the operation to the memory the type; The address decoding register uses in preserving the address which visits and produces the corresponding decoding gating signal. The main equipment through 8 I/O port time sharing multiplying visit component order, the address and the data register, completes visit to chip internal memory’s.
4 K9F1208 reads/writes with cleaning operation realization
Mainly has a page of read and the page programming operation regarding the K9F1208 operation. Figure 3 is the NAND Flash standard page read succession chart. The concrete page read operation is as follows: Sends the order stage, in selects patches or strips of land as worth saving for seed in the signal CE effective situation, first orders permission signal CLE to be effective, write signal We are this time effective, the chip prepares signal R/B to set high, indicated that prepares; Meanwhile reads the operational order to the I/O mouth transmission (0×00 or 0×01), the expression reads the operation. Sends the address stage, this time selects patches or strips of land as worth saving for seed effectively, address permission signal ALE is effective, write signal WE maintains effective, transmits 4 address characters continuously; After the K9F1208 address register receives the address value, the R/B signal will maintain “busily” period of time, hereafter R/B becomes prepares the condition. Finally is the data output stage, each time reads when the desired signal sets is lowly effective, will output a group of data. So the reciprocation finished until all data output.
Figure 4 is the NAND FLash standard page programming succession chart. The concrete page programming operation is as follows: Sends the order stage, operates the first order character to the I/O mouth transmission page programming (0×80), the expression is the page programming operation. Sends the address stage, transmits 4 address characters continuously, after the K9F1208 address register receives the address value, waiting receive data; After data bus transmission data, K9F1208 receives the data continuously, until receives the page programming the second order character (0×10), namely conclusion waiting receive data condition; The R/B signal will maintain “busily” period of time, hereafter R/B becomes prepares the condition. Finally on the main line sends out reads the condition order character (0×70), then the K9F1208 order register receive and the sound should order, operates the successful condition data to the I/O mouth transmission expression (0×00) or the expression operation defeat’s condition data (0X01).
5 uPSD3234A and K9F1208 connections
5.1 hardware parts
uPSD3234A data bus DATA0~7 in direct connection K9F1208 data line. K9F1208 reads/writes a letter the number is reads directly through uPSD3234A/writes a letter the number actuation, the K9F1208 ALE address permission signal, the CLE order permission signal, selects patches or strips of land as worth saving for seed enables the signal by uPSD3234A P43, P44, P45 to control separately, but the K9F1208 R/B condition output signal reads by uPSD3234A P46. Hardware connection as shown in Figure 5. Situation which connects according to this hardware, in the actuation process, may define an invalid address in uPSD3234A, through carries on the read-write to this invalid address to control WR and the RD signal.
5.2 software parts
This design’s driver operates the API function including the basic operation function and Flash. Basic operation function including input functions and so on order value, entry address value, data-in value, read data value and read condition. Because K9F1208 is the non-address, therefore defines an exterior memory’s blank address to come first to carry on writes spatially with reads spatially. The definition sentence is:
xdata unsigned char rK9Fl208DATA _at_0×5000000;
According to the hardware connection diagram, the basic API function’s procedure is:
(1) input order value function
Procedure explanation: Entrusts with P4_5 is 0, causes the CE signal to become the low level, thus selects patches or strips of land as worth saving for seed K9F1208 to be effective; Entrusts with P4_4 is 1, causes the CLE signal to become the high level, thus causes K9F1208 the order permission signal to be effective; Entrusts with P4_3 is 0, causes the ALE signal to become the low level, thus causes K9F1208 the address permission signal to be invalid; Finally carries on to rK9F1208DATA writes the order character spatially, causes the WE signal to become the low level, the K9F1208 order register receives from the data bus to the order character, and carries out the corresponding operation.
(2) entry address value function
Procedure explanation: Entrusts with P4_5 is 0, causes the CE signal to become the low level, thus selects patches or strips of land as worth saving for seed K9F1208 to be effective; Entrusts with P4_4 is 0, causes the CLE signal to become the low level, thus causes K9F1208 the order permission signal to be invalid; Entrusts with P4_3 is 1, causes the ALE signal to become the high level, thus the K9F1208 address permission signal is effective; Finally carries on to rK9F1208DATA writes the address character spatially, causes WE the signal to become the low level, K9F1208 receives from the data bus to the address character, and the lock saves to the address latch.
(3) data-in value function
Procedure explanation: Entrusts with P4_5 is 0, causes the CE signal to become the low level, thus selects patches or strips of land as worth saving for seed K9F1208 to be effective; Entrusts with P4_4 is 0, causes the CLE signal to become the low level, thus causes K9F1208 the order permission signal to be invalid; Entrusts with P4_3 is 0, causes the ALE signal to become the low level, thus causes K9F1208 the address permission signal to be invalid; Finally carries on to rK9F1208DATA writes the data spatially, causes WE the signal to become the low level, K9F1208 receives from the data bus to the data, and according to orders the data which the register and the address latch process receive.
(4) read data value function
Procedure explanation: Entrusts with P4_5 is 0, causes the CE signal to become the low level, thus selects patches or strips of land as worth saving for seed K9F1208 to be effective; Entrusts with P4_4 is 0, causes the CLE signal to become the low level, thus the K9F1208 order permission signal is invalid; Entrusts with P4_3 is 0, causes the ALE signal to become the low level, thus causes K9F1208 the address permission signal to be invalid; Finally carries on to rK9F1208DATA reads the data spatially, will cause RE the signal to become the low level, K9F1208 will act according to orders the register and the address latch comes to the data bus transmission corresponding data.
(5) read function of state
Procedure explanation: Is only reads P4_6 the condition, judges K9F1208 whether “busy”. If P4_6 is the high level, then expressed that K9F1208 is not busy, returns to the high level; If P4_6 is the low level, then expressed that K9F1208 “busy”, returns to the high level.
To operate K9F1208 reasonably, but also increased has not selected K9F1208 the function, in order to after page read and page programming operation, caused K9F1208 not to work. The procedure is only lets P4_5, P4_4, P4_3 is the low level, thus causes K9F1208 to select patches or strips of land as worth saving for seed the signal, the order permission signal, the address permission signal to be invalid. The great definition sentence is as follows:
#define flash_inactive () {P4_5=0; P4_4=0; P4_3=0;)
Flash operates the API function including to reposition K9F1208, to confirm K9F1208 the ID number, to clean K9F1208 some sector, to collect takes the K9F1208 some sector data and reads in functions and so on K9F1208 some sector data. Because of the length relations, only introduces the page read and the page programming function.
Figure 6 is reads K9F1208 some sector or some page of data flow chart. First, starts to K9F1208 transmission page read order character 0×00, causes K9F1208 the order register to receive the order character; Then obtains must read the sector the address, transmits 4 address data continuously to K9F1208, after transmitting, reads K9F1208 the R/B pin condition, not busy (expression address data has received until K9F1208 finishes); K9F1208 starts the sector which reads this address to refer to, and transmits a sector to the data bus the data, this time reads K9F1208 the data bus, finished until the full page.
Figure 7 is reads in K9F1208 some sector or a page of data flow chart. First to K9F1208 transmission page programming’s order character 0×80, causes K9F1208 the order register to receive the order character; Then obtains must read in the sector the address, transmits 4 address data continuously to K9F1208, after transmitting, reads K9F1208 the R/B pin condition, not busy (expression address data has received until K9F1208 finishes); The K9F1208 preparation receives a sector from the data bus the data, this time transmits a sector to the K9F1208 data bus the data, lets K9F1208 receive the data, coexists to the corresponding page or the sector; After treating the transmission the data had ended, to K9F1208 transmits the 0×10 order, caused K9F1208 to finish the page programming operation; Finally receives the order character after K9F1208 transmission inquiry condition’s order character 0×70, K9F1208, to the data bus will transmit a byte the data, by now read K9F1208 the data bus, if receives byte 0×00, then indicates operates successfully, if receives byte 0×01, then expression operation defeat.
Conclusion
This article introduced Samsung Corporation K9F1208 chip characteristic, and has based on this designed based on the uPSD3234A actuation design. This method is related in SoC to other to realize the NAND Flash control method design to have the direct reference significance, but widely applies in needs the big storage capacity in the low end equipment.
