Abstract: Separately based on Hynix Corporation’s SRAM HY64UDl6322A and DRAM HY57V281620E, introduced uses two kind of different RAM structures, designs and realizes the large capacity FIFO method through CPLD.
Key word: SRAM; DRAM; CPLD; Large capacity FIFO
1 introduction
FIFO (First In First Out) is one kind has advanced leaves the memory function the first part, usually serves as the data buffer in the middle of the high speed figure system. In high speed data gathering, the transmission and in the real time display control domain, often needs to carry on the high-speed storage and the read to the mass data, but this kind advanced leaves the first unique feature adapted these requests well, is traditional RAM is unable to achieve.
Many systems need large capacity FIFO to take the buffer, but as a result of the cost and the capacity limit, often uses many FIFO chip cascade to expand, this often causes the system structure to be complex, the cost is high. This article aims at Hynix Corporation’s two section of SRAM and the DRAM components separately, introduced uses CPLD to carry on the connection connection and the programming control, constitutes the low cost, large capacity, the high velocity FIFO method. This method has the versatility, may transplant conveniently to and the other RAM component connected application.
2 with realize based on the SRAM design
2.1 SRAM structure chip HY64UDl6322A
Static state random access memory SRAM (Static Random Access Memory) is one kind of very important volatility memory, its speed is quick, and can in time the fast read and refurbishing maintains the data integrity. This system SRAM component uses Hynix Corporation’s HY64UDl6322A. HY64UDl6322A is high speed, ultra low power loss 32Mbit SRAM, the interior has 2 097 152 16 bit character capacity. Has used the CMOS fabrication technology, the TTL level connection as well as the three states of matter output, has the big input voltage and the temperature range. Simultaneously HY64UDl6322A supports DPD (Deep Power Down) the pattern, guaranteed it in waits for an opportunity under the pattern the power loss to further reduce.
2.2 system hardware designs
The overall system uses CPLD to take the control core component. CPLD selects Altera Corporation’s MAX7128AETCl00-5. MAX7128 based on Altera a Corporation second generation of MAX product structure, uses CMOS EEPROM technical manufacture EPLD, it integrated 2 500 available gates, 128 great units as well as 100 I/0 pins.
Figure 1 is the HY64UDl6322A internal structure as well as with the CPLD connection design system connection diagram. May see, HY64UDl6322A by the address decoding, the logical control module as well as the large capacity memory array is composed. CPLD receives the FIFO control signal, completes the corresponding read-write operation according to this SRAM read-write succession request, through constructs FIFO again the data feeds output and the state control connection returns.
2.3 indicator algorithmic routine design
The system uses CPLD to take the master switch. According to the FIFO characteristic, needs to save SRAM according to the address the structure which advanced leaves first with the programmed control. Here uses the indicator algorithm to realize this kind of structural design: Establishes two pointer variable StartPos and EndPos, separately as data input from beginning to end indicator. When has the recent data reads, the data from the previous secondary storage rearmost position’s next position starts to deposit, stores a data, EndPos on automatic Canada 1, maintains with the final data position synchronization. When EndPos surpasses entire RAM maximum capacity (RAM_SIZE), needs to circulate the returns, from 0×000 position depositing, yizhi dao EndPos and the StartPos superposition, might think that by now RAM already saved fully. When likewise, readout, reference StartPos automatic Canada 1. When StartPos surpasses entire RAM the maximum capacity, from the 0×000 position read, yizhi dao StartPos and the EndPos superposition, might think that by now RAM already read spatially. In the middle of these two processes, CPLD needs to carry on the control to the address wire, is not difficult to discover, writes the data time Address to be consistent with EndPos, reads the data time Address to be consistent with StartPos. Figure 2 is the overall system writes and reads the sequential control the flow chart.
2.4 sequential control
Write data time, CPLD needs to simulate FIFO basically to write the operation succession: CPLD receives nWEN (to write enables, low effective) and WCLK (writes clock, rises effectively along), namely, when nWEN is low, WCLK is the rise along, reads in the current I/O on data. In the data reads in RAM time, CPLD should defer to HY64UDl6322A to write the succession to control writes the operation. Here, CPLD first defers to above flow to calculate the address which the current data should deposit, then controls the nWE signal, nWE is when is low, the data automatically reads in RAM. Then writes down bit data again. Entire writes succession as shown in Figure 3.
Likewise, CPUD receives nREN (to read enables, low effective) and RLCK (reads clock, when rises effectively along), will read in first data read-out. Here, CPLD first defers to reads the data flow to calculate the current readout depositing address, then controls the nOE signal (low level effective), the data reads out RAM automatically. Then carries on the next bit data to read again
Leaves the operation.
May see, affects constructs the FIFO read-write speed the key aspect is tWC, this parameter is also decides the HY64UDl6322A speed the primary factor, therefore, constructs FI-F0 the theory speed to approach HY64UDl6322The speed.
3 with realize based on the DRAM design
3.1 DRAM structure chip HY57V281620E
Generally speaking, dynamic random access memory DRAM (Dynamic Random Access Memory) is with uses for the supporting logic circuit which by the big rectangle memory cell array reads to the array and writes, as well as the maintenance stored datum complete refurbishing electric circuit composes. Although operates compares SRAM to be complex, but because DRAM has each memory bit cell low cost and the high density merit, enables them to become the commercial domain most widespread use the semi-conductor memory. This system’s DRAM chip uses Hynix Corporation’s 134 217 728 bit synchronized DHY57V281620E. It is composed of 4 2 097 152×16 bit. Has used the CMOS fabrication technology, the LVTTL level connection.
3.2 system hardware designs
Similarly uses MAX7128AETCl00-5 to complete the systems control. Figure 4 is the HY57V281620E internal structure as well as with the CPLD connection system connection diagram. Interface control principle similar 2.2 state. What is different, the HY57V281620E interior by the ranks address decoding, many large capacity memory cell array and some logical control module is composed.
3.3 programmings
Here, mainly uses in 2.3 to set up from beginning to end two indicator’s thought. Is different what with SRAM, DRAM uses the rectangle memory cell array is controls by the good line and the alignment, and the interior uses the piecemeal structure, here HY57V281620E is composed of 4 memory cells, controls through BAl and BA0. In writes the data manipulation, when the depositing data length surpasses the current memory cell capacity, needs the CPLD cut to carry on the memory to the next memory block, similarly, reads the operation time also has this kind of operation, namely, if StartPos or EndPos have surpassed the memory block capacity, here is 2 097 152, through a mold 4 counter control cut to next memory block.
3.4 sequential control
Reads in (or read-out) data time, CPLD needs to simulate FI-FO basic to write (or reads) operates the succession: CPLD receives nWEN(nREN) and WCLK(RCLK), namely, when nWEN(nREN) is low, WCLK(RCLK) is the rise along, reads in (read-out) the current I/O on data. In the data reads in (read-out) RAM time, CPLD should defer to the HY57V281620E component to write (reads) the succession to control writes (reads) operates: CPLD first controls nRAS from the high level changes to the low level, chooses the good address. Through controls a nCAS choice row address again. Here, when reads in (or read-out) the data in with middle carries on together, may maintain the nRAS low level, the sampling multi-row data manipulation (is also called as quick page pattern read-write). When the data address surpasses the block capacity, then needs to choose the good address, then carries on continuously the multi-row data read-write operation again. The read-write enables the control and SRAM is similar, (low effective) controls through nOE and nWE.
Figure 5 is the DRAM main read-write control succession. May see, affects constructs the FIFO read-write speed the primary factor is tPC, this is also decided that the DRAM speed the key is, therefore, constructs FIF0 the theoretical velocity also to approach the DRAM upper frequency. At the same time, but must consider DRAM the refurbishing operation. Here, the system uses nCAS is before nRAS way (CBR), namely controls nCS, nCAS, nRAS, and maintains nWE is the high level, the use chip interior counter decision must by the refurbishing line. HY57V281620E provided this kind from the refurbishing pattern, the refurbishing speed had decided by tREF that usually was 64 ms. In the system or in some memory length time no-operation’s situation, needs fixed time refurbishing, maintains the data is complete.
4 experimental results and analysis
Figure 6 is with QuartusⅡthe succession profile which 4.O acts according to 2.3 to set up the indicator algorithm design simulation which from beginning to end comes out.
May see, the system starts from the 0×000 bottom to write the data, when reads in 3 data, EndPos increases Ox003, carries on 3 data to read the operation again, namely StartPos increases 0×003, this time, constructs FIFO reads the dummy status, may see read spatial signal Empty to become the high level by now, achieved the FIFO design to need to ask.
Also needs to pay attention: Because uses RAM only uses a data bus to take the input output, therefore in writes the data time cannot carry on reads the operation. But the commonly used FIFO component may simultaneously the read-write. Therefore, if must carry on during the same period of time reads and writes the operation, then the need carries on the read-write in a FIFO read-write clock cycle to RAM and so on many operations, by now constructed the FIFO speed will reduce.
In addition, when constructs high speed FIFO with DRAM, because the memory block choice needs certain time operation, therefore cross block store operation compares Gao Shi in the frequency will affect the normal data read-write, will have the individual data missing situation. Moreover when some period of time carry on the refurbishing operation, has the sharp-edged data to need to read or to write, by now did not permit the interrupt. Solves this question means is FIFO which marks with I/O pin (nREADY) current constructs whether may the read-write, if has the above situation occurrence, then nREADY is high, may when the read-write for low.
The commonly used FIFO component also has half-full, close full, close spatial and so on status indicators, may, in above constructs FIFO in the foundation to add on the simple logical control, calculates between StartPos and the EndPos differential value, is writes the operation according to the present or reads the operation to instruct. Other status signal may also realize very conveniently through CPLD by way of the logic operation. At the same time, reads and writes the synchronized clock to be possible not to be inconsistent, like this may constitute the synchronization or asynchronous two kind of FIFO very conveniently, has the very good extendibility.
5 concluding remark
Now, the SRAM data transfer rate may achieve in 10 ns, DRAM must be slightly slower than SRAM some. Therefore, SRAM usually uses in the high speed cushion saving, but DRAM usually uses for to save the big data. Considered from the cost that DRAM must lower a lot compared to the SRAM cost.
Uses structure which and design concept this article gives, avoided formerly advocating CPU took over control when RAM a series of complex read-write operation, but direct similar FIFO use, connection simple convenient, and has avoided the traditional FIFO component capacity and the cost limit. This article through the theoretical analysis, the actual circuit design debugging, has succeeded realizes constructs FIF0 with two kind of different structure RAM, and using in many real-time high speed signal gathering system.
