The abstract introduced that one kind requests in view of timeliness to compare Gao Qie to process the data quantity big system’s design and the development plan. This plan uses high performance AVRATmegal28 is its control core, realizes in 512 KB SRAM data which outside the visit expands, and in power failure time outside can protect expands in SRAM the data. When exterior power failure, forewarns the circuit protection field data in SRAM which expands to outside, by the lithium battery the SRAM power supply which expands for outside; When outside normal power supply, according to needs to charge by DSl302ZN to the lithium battery. This plan after the actual movement, proved that its design is feasible.
Key word AVR ATmegal28 expands 512 KB the SRAM power failure data protection
Now, the electronic technology development is swift and violent, particularly the monolithic integrated circuit widely has applied in domains and so on correspondence, transportation, domestic electric appliances, portable intelligent measuring appliance and robot manufacture, the product function, the precision and the quality has the large scale enhancement, and the electric circuit is simple, the failure rate is low, the reliability is high, low in price. In monolithic integrated circuit’s certain applications, if does not carry on the expansion to system’s exterior SRAM, cannot satisfy the system design the request. How therefore to expand, expand the question which any type the chip, the expansion capacity many greatly becomes is worth considering. This question solution good and badly direct relation project success or failure. This article introduced how to realize 512 KB SRAM plan which in AVR ATmegal28 the expansion power failure data does not lose.
1 system hardware structure
What the monolithic integrated circuit uses is Atmel Corporation produces ATmegal28, its pin arrangement like chart l shows. The ATmegal 28 monolithic integrated circuits for based on AVR RISC the structure 8 low power loss CMOS microprocessor, rely on the advanced set of instructions as well as the monocycle instruction time, its data turnover rate reaches as high as 1MIPS/MHz, may alleviate between system’s power loss and the processing speed contradiction. The AVR monolithic integrated circuit essence has the rich set of instructions and 32 general working register, all registers directly connect with arithmetic logic unit (ALU), cause an instruction to be possible simultaneously to visit two independent registers in a clock cycle. This kind of structure raised the code efficiency greatly, and has compared to the ordinary complex set of instructions microprocessor high 10 time of data volume of goods handled. ATmegal28 monolithic integrated circuit built-in: Ability which 128 KB in the system programmable Flash program memory, has in writes in the process which may also read, namely at the same time read-write (RWW); 4 KB EEPROM; 4 KB SRAM; 53 general I/O port line; 32 general working registers; Real-time clock (RTC); 4 nimble have the comparison pattern and the PWM function timer/counter (T/c); 2 UJSART; Face byte two connection (TWI); 8 channel 10 ADC; May elect programmable gain; Internal oscillator’s programmable watch-dog timer; Serial auxiliary equipment connection (SPI); With IEEEll49.1 the standard compatible JTAG test connection, at the same time this connection may also use on the piece debugging; 6 kinds may the province electricity pattern which chooses through the software.
The SRAM interface circuit is composed of latch 74AHC573D and BS62LV1006SIP55, as shown in Figure 2. The XRAM connection’s operating frequency is very high, when system’s working condition is higher than 8 MHz@4 V (4 V supply voltages, 8 MHz operating frequency) and 4 MHz@2.7 V (2.7 V supply voltages. When 4 MHz operating frequency), must carefully the select address latch. This time, the typical 74HC series latch already was unable to satisfy the request. XRAM connection and 74AHC series latch compatible. BS62LV4006SIP55 is the BSI high efficiency, the low power loss CMOS static state direct access storage device, can adapt 2.4~5.5 V wide range working voltage, has the model CMOS high efficiency low power loss characteristic; Under 3.0V/25℃ condition electric current for 0.25μA, under 3.0V/85℃ the condition, the longest access time is 55 ns. Through selects patches or strips of land as worth saving for seed the CE signal, the output to enable the OE signal and the three states of matter output actuation, may carry on the SRAM expansion very conveniently. When BS62LV4006SIP55 is in has not selected patches or strips of land as worth saving for seed the condition, it has automatically reduces the power loss the characteristic.
The power failure data protection electric circuit by the SA56600-42D interface circuit, the DS1302ZN interface circuit and the early warning comparator is composed, electric circuit schematic diagram as shown in Figure 3. What SA56600-42D is Philips Corporation produces is protects in SRAM the data integrated chip; DS1302ZN is real-time clock (RTC) which DALLAS Corporation produces, but it also has the programmable control battery charger’s function, can carry on the control charge through the 8th foot for the lithium battery; The early warning comparator has protects the field data the function, when the external voltage is lower than 10V, will simulate the comparator to trigger the interrupt, will thus protect the field data outside expands in SRAM or EEPROM.
2 principles of work
In main function main(), to the I/O mouth, the timer, a/D switch, simulates the comparator, RTC DSl302 and outside expands SRAM and so on to carry on the initialization. Expands outward when SRAM carries on the visit, through the PD5~PD7 definite page address, acts according to A, the C second function to visit exterior SRAM again to assign the address, this part has the simple example in the procedure detailed list. Some point must pay attention, after the exterior memory maps the internal memory, MCU can only visit each page under the default condition 60 KB exterior memory (address 0×0000~0xlOFF is internal memory retention). However, may visit the entire 64 KB exterior memory using the shield high address method. This wants the special attention regarding the cross page visit.
In the timer interrupt routine, every other a section of hypothesis’s time must transfer A/D to transform, obtains lithium battery’s voltage. To the lithium battery voltage which obtains carries on processing in a/D interrupt processing function. If obtains lithium battery’s voltage is lower than an hypothesis the value, then transfers DSl302 the 90H order to carry on the charge to the lithium battery; If the lithium battery voltage is higher than the hypothesis the value, then transfers DSl302 the 91H order, obtains the register to correspond the TCS3~TCSl position the value, judges DS1302 whether to battery charge. If in the charge, withers with the DSl302 90H order, finished to the battery charge.
When in the early warning comparator the ATNl voltage is lower than AIN0, triggering simulation comparator interrupt. In this interrupt processing function internal SRAM data backup to exterior SRAM or EEPROM, because thus prevents the external power supply power failure to create the data missing.
When the external power supply power failure or restores supplies power, outside the SA56600-42D automatic cut over will expand SRAM the power supply. When the external voltage is lower than 4.2 V, outside SA56600-42D will make to expand SRAM to be at has not enabled the condition, will enable SRAM to visit; When the external voltage is lower than 3.3 V, the SA5660042D automatic cut over lithium battery will expand the SRAM power supply for outside, will achieve outside the protection to expand in SRAM the data same; When the external voltage is higher than 4.2 V, the SA56600-42D automatic cut over main power source will expand the SRAM power supply for outside.
3 system’s merits
①Use high performance RISC construction AVR the ATmegal28 monolithic integrated circuit, has overcome the traditional monolithic integrated circuit from the hardware in the handling ability, in the periphery connection ability insufficiency, may realize the complex programmed control.
②Outside expands SRAM to achieve 512 KB, broke the traditional 64KB addressing range limit. This has the very vital practical significance to the monolithic integrated circuit.
③Outside expands SRAM, and realizes the power failure data protection function. Is opposite in expands EEPROM the system, this system’s response wants quickly many.
④Using this plan, does not need to use the ARM microprocessor in certain application aspect, thus achieves reduces the system cost and the development difficulty goal.
The procedure detailed list sees this publication website www.mesnet.com.cn - - editor note.
Conclusion
Uses this system’s expansion exterior SRAM plan, both can guarantee system’s speed of response, and can guarantee the data the security. This design proposal has the hardware architecture to be simple, the cost low status superiority, in the demonstration, the pronunciation, the traffic control and aspects and so on intellectualized parking lot management system management system, has certain reference value. After some parking lot intelligence management system management system’s actual movement, proved that this design proposal is successful.
