This article has designed on the 1553B main line’s network memory. The overall system based on the NIOS II essence design, integrates completely using the SoPC technology the connection part’s logical control in FPGA internal, system’s reserves, point quantity may expand.
In the 1970s was born the 1553B main line, was one kind of host from the type redundancy main line, had the strict stipulation to the bus hardware, the reliability and timeliness is good, already became now the military electronic main line’s first choice. Is similar in the ethernet, in the 1553B network also has “the network hard disk” such memory demand, reduces the local memory pressure, and may supply other part of even other network use as data relaying.
The Nios II embedded processor is Altera Corporation the second substitution which promoted in June, 2004 the soft nuclear processor which might dispose in the programmable logical component, the performance surpasses 200 DMIPS. Nios II is based on the Harvard structure RISC general embedded processor soft nucleus, can unify with the user logic, programs to Altera FPGA. The processor has 32 sets of instructions, 32 bit data channels and may dispose instruction as well as data buffering. It has carried on the optimization design specially for the programmable logic, also (SoPC) has designed a set of comprehensive solution plan for the programmable single chip system.
Figure 1 system hardware structure diagram
System overall concept
This system’s major function to receive the order which, the data the 1553B network sends, after the management, the level memory, provides a reference to storage’s network interface. System’s memory interface takes in the 1553B main line from the point, usually is at the readiness for action, when on the main line has the read-write orders to send, the main line transforms the connection basis order after the level memory read data or to its write data. Regarding main line agreement, what is most convenient is the use ready-made agreement chip, but does the cost is high, the 1553B agreement chip’s monolithic price above 6000 Yuan, this regarding the ordinary application is not a small burden, if can use FPGA to carry on the agreement management, will cause the cost to reduce greatly, moreover, the Quartus intension includes the IP endorse which many memories manage to supply the use, needs independently to have custom-made the module regarding the 1553B agreement.
The system program is two parts, a part to accept the network order and the data, another part for memory’s read-write. In NIOS in the IDE environment, uses the C language to take the programming language.
System hardware design
System’s hardware module diagram see Figure 1 to show.
System’s core chip uses Altera Corporation’s CYCLONE III series FPGA EP3C25F324. It used the 65nm low power loss processing technology to carry on the production, its integration rate and the performance had enhanced obviously, but the power loss was actually low, in addition the CYCLONE series has located in the low cost component, the chip whole performance-to-price ratio is very high.
Software transplants the Nios II essence through Quartus II 7.2 integration’s SOPC to the FPGA interior, needs the module to be as follows.
* CPU: Selects the standard CPU nucleus, Debugger is Level 1, in meets the need in the situation to save the internal resources use as far as possible.
* System_ID: When downloading when system authentication uses.
* Jtag_uart:FPGA and the PC correspondence connection, NIOS in the IDE software the use will be very convenient.
* onchip_memory: The internal memory, relays when the data uses.
* FLASH:Quartus software interior integration
Figure 2 1553B main line’s three kind of frame structure
Has the 128P308 control assembly which Intel Corporation produces, is advantageous for the development, if need more massive memories, enlarge the FLASH capacity then, if has the need, may hang several pieces.
* the FLASH_Bus:FLASH data is the three states of matter, needs joins the Avalon three states of matter main line bridge between CPU and FLASH.
* 1553B connection module: With exterior 1553B main line correspondence’s connection, the Quartus software interior integration has not had this module, needs to develop voluntarily.
In the 1553B network, this system takes from the point design. In the system, the 1553B connection module needs to take on the Alavon main line’s main port, other memory control module takes from the port. Because other ports have the integration in the Quartus software interior, therefore, the system software design’s main work load is the 1553B connection module development.
The memory chip uses the 128P308 FLASH chip which Intel Corporation produces, conforms to the general interface standard, is advantageous for the following function capacity the renewal promotion.
Figure 3 FPGA interior work flow
System software design
Has custom-made the 1553B module’s core duty is the 1553B main line signal conversion to NIOS on II internal Avalon main line.
the 1553B module takes on the Avalon main line’s main port, selects the signal has clk, address, read, write, data, irq, reset, irqnumber and so on. The transmission mode reads the transmission for the basic main port and writes the transmission. Produces these signals to need the frame signal which reads from the 1553B main line to realize. on the 1553B main line altogether has three kind of frames, the order frame, the condition frame and the data frame. These three kind of frame’s structure as shown in Figure 2.
Regarding these three kind of frames, the order frame, the data frame and the condition frame may use the identical buffer, because of as the memory from the point to the major node transmission data, the entire work will not be the passive receive major node order on own initiative, will wait for the major node read or the write data, the system only then the sole condition, will not present the conflict.
Regarding the Avalon main line’s in signal, corresponds in the frame the signal relations are as follows.
* read/write signal: Orders in the frame the transmission/receive position.
* address signal: Orders in the frame the sub-address as well as the data length position.
* data signal: In data frame data position.
* irq signal: In the condition frame’s flag bit causes.
* irqnumber signal: In condition frame concrete position.
1553B module’s API function includes:
* altera_avalon_1553B_init()
* altera_avalon_1553B_enable()
* altera_avalon_1553B_disable()
* altera_avalon_1553B_getframe()
* altera_avalon_1553B_sendframe()
Other have custom-made module’s step no longer to give unnecessary detail. The module completes after the SoPC definition, the naming is 1553B, increases to the NIOS II essence.
FPGA internal work flow as shown in Figure 3.
The system usually is at the readiness for action, when order frame arrival will cause the interrupt, will interrupt the sub-regulation namely through altera_avalon_1553B_getframe() explanation order frame content, the determination is the read or reads, the read or write data’s length, the data characteristic will take the next time read the symbol, after truly unmistakable, will start to read or to read.
Memory’s management different has two points with other applications in: After each time reads, must the data which reads in do a sign, by facilitates the later read; Moreover, but must calculate the surplus memory the capacity, when next need write data judges whether can under the accommodation this secondary storage. the 1553B major node after the use finished the data also needed to provide the signal to come the clear spatial memory to release the resources.
