Abstract: Introduced that one kind based on the digital signal processor (DSP)TSl01 chain street intersection’s multichannel high accuracy data acquisition electric circuit’s design method, the detailed elaboration uses many ADS8361 a/D switch to carry on the data acquisition, and transmits orally after the TSl01 link loses the data FP-GA and the DSP design realizes, how discusses to increase a/D conversion accuracy the question.
Key word: TSl01; Chain street intersection: ADS8361; Sampling precision
1 introduction
In the signal processing domain, the DSP technology’s application is getting more and more widespread, processes the platform based on the DSP signal gathering to appear unceasingly. Common DSP signal gathering processes the platform to carry on the data acquisition using the main line, on the main line many equipment’s data transmissions conflicts mutually frequently. ADI Corporation’s Tiger SHARCl01 DSP (i.e. TSl01) only then the main line and the chain street intersection might with the peripheral device correspondence, based on the alleviation main line conflict goal, the author design one kind to take the data interface buffer by scene programmable gate array (FPGA), avoided the main line, will be many after the TSl01 chain street intersection data transfer TSl01 which a/D switch gathered. Completes many multi-channel A/D switch gathering data by FPGA cushion sorting, and forms conforms to the TSl01 link to transmit orally loses the agreement the data stream, delivers TSl01 the chain street intersection. This design has realized the chain street intersection and other non-chain street intersection external instrumentation’s correspondence. Reduced on the TSlOl main line’s data transmission capacity, alleviated the main line competition question.
2 ADS8361 A/D switch
ADS8361 is the double channel which, four groups, the simulation differential input, 16 bit TI Corporation produces the synchronized sampling serial A/D switch. 4 group simulation differential input divides into 2 groups, each group has 1 A/D transformation module respectively, may simultaneously the sampling; May realize 500 ks/s sampling rates most quickly to each input, namely 2 μs complete 1 A/D sampling. After the sampling data by the serial interface output, this regarding has synchronized serial interface majority DSP is very useful, the DSP main line may hang meets many kinds of other equipment, in the high speed continuous sampling’s process, the DSP serial port and the main line may not interfere with the independent working mutually.
ADS8361 when the sampling frequency rate is 50 kHz, some 80 dB syntype suppresses, this is important in the strong noise environment. ADS8361 needs the analogue voltage and the digital voltage supplies power separately, considers with the exterior electric circuit’s match, therefore the simulation part chooses 5 V power supplies, the numerical part is consistent with the DSP I/O voltage, chooses 3.3 V power supplies. When work already may use the interior 2.5 V reference voltages, may also provide the reference voltage by exterior. Difference analogue input signal voltage range for ±2.5V. ADS8361 uses the SSOP-24 seal. The CS pin is ADS8361 selecting patches or strips of land as worth saving for seed; Ml, M0, the AO pin uses in choosing the sampling channel and the data channel; The RD pin into the read data pin, the CONVST pin is a/D switching pulse, should is connected in the use RD and the CON-VST pin; The CLOCK pin uses in inputting the sampling clock (and in as follows FPGA output ADCLK connected); 2 channel’s data output pins respectively are SERIAL DATA A and SERIALDATA B, each time transforms outputs 16 bit data. The ADS8361 work clock maximum value is 10MHz, high level and low level at least each 40 ns.
3 TSl01 chain street intersections and transmission mode
TSl01 is the high performance 128 bit floating point digital signal processor, its operational capability is very strong (for 1,800,000,000/seconds), but external bus handling capacity is relatively insufficient (, if the exterior frequency is 100 MHz, then external bus transmission speed is 800 MB/s), when the peripheral device are many are very easy to form the I/O bottleneck. However its four high speed chain street intersection, each chain street intersection’s transmission speed limit is 250 MB/s, suits between TSl01 the point-to-point high speed transmission, may also with its same agreement peripheral device correspondence, thus alleviated the main line pressure greatly.
The TSl01 each chain street intersection is composed of the transmitter and the receiver two parts, each part has 128 bit shift registers and 128 bit cushion register, its structure like chart l shows. Each chain street intersection has 8 bit data lines and LxCLKIN, LxCLKOUT and LxDIR (x for chain street intersection serial number 0-3) 3 control pins, may support between many piece of TSl01 processors the point-to-point bidirectional data transfer, may also use in with the external instrumentation carrying on the data transmission. And LxDIR uses for to instruct that the chain street intersection the data flows. LxCLKIN and LxCLKOUT are the chain street intersection clock/confirmation handshake signals. When transmits the data, LxCLKOUT is the clock signal, LxCLKIN is the confirmation signal; When receives the data, LxCLKIN is the clock signal, LxCLKOUT is the confirmation signal. When transmits the data, first transmits 4 character data to link transmission cushion register LBUFTx, then duplicates it the shift register (, if shift register for spatial, this time LBUFTx may read in recent data), then (transmits low byte first) by the byte form transmission, each byte along along is actuated in the link clock’s rise with the drop and the lock saves. Receiver’s shift register will be the free time, the system will start to receive the transmitting end transmission the data and sends in it the shift register, simultaneously will actuate LxCLKOUT is the low level. After the entire 4 character receive finished, if receive cushion register LBUFRx were spatial, the system will duplicate 4 character data from the shift register to LBUFRx, and after the data is duplicated actuated its Lx-CLKOUT is the high level, take told the transmitting end receive cushion register as spatially, might prepare to receive the recent data. After the transmitting end examines Lx-CLKIN is the high level, carries on the next time transmission immediately.
The common start link transmission data’s method has two kinds: And uses the link interrupt enable inte using the TSl01 IRQ interrupt enable inte. The link transmission carries on by the DMA way, the DMA way is in the TSl01 essence does not intervene in situation, backstage through chain street intersection high speed transmission data mechanism. Transmits orally from the external instrumentation to the link delivers the data, in fact is the chain street intersection the data which sends the external instrumentation preserves automatically TSlOl, in the external memory, may also pass through other chain street intersection to retransmit. Carry on the correct establishment after the chain street intersection and the DMA register may establish the TCB block. After DMA start, once link buffer not full, it to external instrumentation request data. By now, DMA if might take the interior or the exterior data bus, that the system then may transmit orally the data from the link delivers in the memory.
4 data acquisition hardware design
TSIOI is the operational capability is strong, but with exterior connection resources relatively few kind of DSP, in many TSl01 level system continually, if carries on the data acquisition using the main line, a/D switch usual need long time takes the main line, will present the struggle to occupy main line’s question frequently, will thus cause signal gathering processing to present the main line bottleneck, will carry on the data acquisition using the chain street intersection to be possible the very great degree release main line resources. In this application needs simultaneously to carry on 500 kHz to 10 group simulated signals the sampling, the transmission data rate is lOx0.5 MBx2=10 MB/s<250 MB/s.
TSl01 carries on the data acquisition through FPGA, its chain street intersection takes the data input port. Their connection structure as shown in Figure 2, chain street intersection LxCLKIN directly with the FPGA connection, by the FPGA actuation, when FPGA transmits orally to the link delivers the data takes the chain street intersection the clock input. LxDIR and LxCLKOUT may be hanging, the chain street intersection’s 8 data lines receive on FPGA.
In the design each/D switch’s M1, NO, a0 pin earth, only uses each/D switch’s 2 simulation differential input - - AO and the B0 channel, 2 channels may in 2μs within simultaneously complete 1 sampling. This design uses in common 5 ADS8361 levels to expand the analog input channel continually, realizes 10 analog channel input, each ADS8361 RD and the CONVST connection, carries on the control by FPGA, 5 ADS8361 simultaneously carries on A/D to transform, after the transformation, simultaneously completes the string in FPGA and transforms, the lock has in first FPGA after the transformation parallel data, then after is first low the byte the high byte in turn transmits various channels to the TSl01 chain street intersection.
5 data acquisition software design
The software part including the TSl01 software design and the FPGA software design, the FPGA software design uses VHDL to realize. Its structure as shown in Figure 3.
The FPGA main operation is 5 ADS8361 10 group serial gathering data conversion 20 8 bit data, saves again the data lock, simultaneously produces the link clock, saves after the lock the data transmits to the TSl01 chain street intersection. Needs to realize succession as shown in Figure 4, CLOCK is the TSlOl external clock, ADCLK is the ADS8361 work clock, is the CLDCK 5 frequency divisions, the dutyfactor is 60%, CONVST and RD connects, LINKCLK is the link clock, LINKDATA is the link data.
When use link transmission, TSl01 along saves the data in the link clock’s rise with the drop along the lock, 20 8 bit data need the lO link pulse, but the chain street intersection each time at least needs to transmit 128 bit data, namely needs 8 pulses at least, and the transmission data needs the pulse number must be 8 multiples. Therefore in the design each time through the link transmission data’s pulse number is 16, first 10 the data which transmits a/D switch to gather, after that 6 pulses transmit 0×55. Transmits to the link data is a/D switch previous transformation result. TSl01 may establish the chain street intersection work clock as the essence clock 2, 3, 4, 8 frequency divisions, in the design TSl01 external clock CLOCK is 50MHz, the essence clock is CLOCK 5 frequency multiplication namely 250 MHz, when the chain street intersection receive data FPGA for TSIOI link clock LINKCLK is 25 MHz the TSl01 chain street intersection work clock should as far as possible close link clock LINKCLK, therefore establishes the TSl01 chain street intersection work clock as essence clock’s 8 frequency division namely 31.25 MHz.
The system uses the link interrupt mode to receive the data which FPGA sends, the link interrupt mode data receive procedure is as follows:
6 A/D switch electric circuit’s design and use
The design high accuracy A/D switch’s key is the guarantee significant digit, the ADS8361 input dynamirange is: ±2.5 V, each quantification unit corresponds 0.076 mV, therefore should try the noise reduction and the disturbance. The noise and the disturbance origin mainly has two kinds: One kind is a/D switch own noise like quantizing noise and so on, another kind the noise jamming which is periphery the electric circuit produces. The former is a/D switch inherent, the latter’s size goes far beyond the former, specially power source, between simulation/electric circuit digital circuit’s disturbance. The ADS8361 differential input way reduced the syntype disturbance greatly. In the design mainly considered how to reduce other noises and the disturbance in the electric circuit.
The power source design is the noise elimination key, the design which this article introduced has many kinds of voltages (to simulate 5 V, - 5 V and digital 3.3 V, 1.2V and so on), and is the hybrid simulation and the digital signal board level design, chooses the appropriate power circuit, carries on the power source level and stratum cutting is reasonably very important. The switching power supply has the volume to be small, the efficiency is high, output stable and so on merits, simultaneously can solve the TSlOl on electricity order problem well, but the ripple is obvious. The turn-on frequency higher output voltage ripple is smaller, in the electric circuit selects inductor in 10μH~200 μH for suitable, in the electric circuit may use ESR to be small, Rong Zhida the capacitor constitution decoupling circuit, simultaneously lays aside many kinds of capacitors on the board to carry on the filter.
The reduction digital signal disturbance may also increase a/D switch’s precision effectively, when the panel and the wiring must make ADS8361 to simulate the difference signal input region to be far away from the digital signal as far as possible, in the FPGA design avoids many signal levels also turning over as far as possible, simultaneously gives a/D switch to provide the good work clock, should use the series connected terminal law, connects 1 small resistor to be possible the very good reduced time base vibration, the clock signal to enter a/D switch’s wiring to be shorter is better, simultaneously do not leave the digital signal to be too near, also do not approach the simulation area, will otherwise increase the simulation area the noise. Simultaneously must pay attention to the simple point altogether, lights in altogether the place serially connects 1 magnetism bead. In the design has used the multiply wood layout, may reduce in the underloading situation the output voltage ripple 4mV.
7 concluding remark
The author designs one kind to carry on the multi-A/D switch multichannel high accuracy data acquisition through the TSl01 chain street intersection to realize the method, may not take the main line in the DSP signal gathering processing system, realizes the parallel data transmission and processing, has a higher timeliness, how simultaneously discussed to increase a/D switch precision the question. This design method already applied in many kinds of parallel and the serial A/D switching circuit, has the versatility.
