Abstract: This article introduced SDRAM controller IP nucleus processes and so on design, electric circuit’s function simulation, synthesis as well as confirmation, discussed this controller’s connection design to realize the SoC integration with emphasis. The performance analysis indicated that this controller rational design, the performance are outstanding. The result had proven this IP conforms to the SDRAM controller technology standard in the function and the succession, has achieved the predetermined target.
Key word: Dragon core, synchronized dynamic memory, on piece system, bus interface
Along with the design and technique of manufacture’s development, the integrated circuit design develops from transistor’s integration to the logical gate integration, now develops the IP integration, namely SoC design technique. SoC may reduce the electronic information system product effectively the development cost, reduces the development cycle, enhances the product the competitive power, is most main product development way which the industrial world will use. At present domestic has also enlarged in the SoC design as well as the IP integration domain research. This article introduces is on the piece which country funding project support’s Long Xin SoC-ICT- the E32 design integrates the SDRAM controller module design with realizes.
1 ICT-E32 architecture
ICT-E32 is section of 32 high performance SoC, its collection Cheng Long core 1 CPU and develops voluntarily on the piece the main line construction, is for the purpose of advancing Long Xin the industrial production, explores the SoC design method. It may use in aspects and so on PDA, intelligent electrical appliances and expense class electronic products, it integrates the platform also to be possible to use in the following chip development, the development derivative product. ICT-E32 uses Long Xin 1 CPU nucleus is section of 32 MIPSCPU. On the piece the main line according to hangs carries IP the band width to divide into two levels, respectively is the high speed main line and the low speed main line. The high speed main line uses the address running water and reads/writes the concurrent technology, the data line width is 64bit, upper frequency 133MHz, hangs has the CPU nucleus, SDRAM Cont roller and modules and so on PCI Controller; The low speed main line uses the Wishbone architecture, data line width 32bit, upper frequency 66MHz, hangs has UART, modules and so on USB Host and LIO connection.
Two levels of main lines through bridge connection. Also some passes through on the piece all IP module main line - DCR (Device Cont rol Register Bus) the main line. This is a ring-like main line, CPU is on the DCR main line the only main equipment, is responsible other equipment carries on the read-write operation to the main line on. The DCR main line uses to each IP module register piles (Register bank) to carry on the read-write. Its approximate structure drawing as shown in Figure 1.
Figure 1 ICT-E32 structure drawing
2 SDRAM controller design with realizes
The SDRAM controller hangs carries on the IC - E32 internal high speed main line, is on main line’s Slave equipment. It supports the SDRAM size scope is 64M~1G. Visits DIMM strip through the I2C serial main line agreement SPD (SerialPresence Detect), disposes the SDRAM controller’s pattern register. Its operating frequency and high speed main line synchronization, compatible PC100/133. The data line width is 64, supports the burst operation (1, 2, 4, 8 with full page), supports the order and visits alternately. The SDRAM controller is mainly composed of three big modules, including high speed bus interface, DCR bus interface as well as SDRAM control module.
2. 1 high speed bus interface
The ICT-E32 internal high speed main line is similar to the IBM PLB main line agreement, its address wire is 32 with the data line is 64. This is on a section of high performance piece the synchronous bus, the clock which on main line’s equipment use identical clock source provides. Uses the two-level address running water and the read-write concurrent technology. Between the Master equipment and the Slave equipment reads by the bus arbitration control bus on/writes the operation. On main line’s Master equipment use monopoly address wire, reads the data line, to write the data line as well as the transmission control signal, but the Slave equipment shares the separation the address and reads/writes the data line, reads/writes the data line to have the respective transmission control signal. It supports the SDRAM arbitration, the arbitration principle is uses the belt grab to eliminate the way, the CPU visit priority is highest.
Interior high speed bus arbitration use static state priority, when the Master equipment sends out the request to some Slave equipment, makes the arbitration by the bus arbitration, if this Master equipment’s priority is highest, makes the reply to this Master equipment, simultaneously issues the order to the Slave equipment, causes it to monopolize the Slave main line.
The SDRAM controller takes on the internal high speed main line’s Slave equipment, only the order which sends out to the main line makes the response. The high speed bus interface is responsible for the order which gives the main line transform into to the SDRAM controller’s operation. When the main line issues the order, the high speed bus interface first judges SDRAM the condition, if the memory is at the idling condition to give the SDRAM controller to send out reads/writes the instruction, in the SDRAM controller completes after the memory operation, returns to the answering signal for the main line and reads the data, reads/writes the data separately after synchronized FIFO and the bus interfacing. Figure 2 (a) has given the high speed bus interface concrete operation flow chart.
2. 2 DCR bus interface
What the ICT-E32 DCR main line refers is the IBM DCR main line. This is a section of 32 synchronous bus, uses for general register and between the Slave equipment’s pattern register transmits the data in Master the equipment CPU, is on a penetration piece all IP module ring bus.
When CPU disposes some Slave equipment’s pattern register, gives the layout data through the DCR main line, simultaneously gives this equipment’s address. The Slave equipment when accepts on the DCR main line’s data, first judges the address whether to correspond, if gives the address accepts the data for own address; If is not, gives data bypass (bypass) the next equipment.
The DCR connection’s function receives various registers’ value which CPU reads, and provides the condition register and other register’s content to CPU. Judges the address through the address comparison logic whether to hit, if the address hit accepts the data, simultaneously gives the answering signal; Otherwise, gives the data bypass on the DCR main line’s next equipment. Figure 2(b) has given the DCR bus interface operation flow chart. 
Figure 2 bus interface operation flow chart
2. 3 SDRAM control module
The SDRAM control module after accepting the system order, is responsible the certificate of deposit sends out to SDRAM in reads/writes the work management signal. Its interior mainly contains the Mealy state machine which a control state transforms, as shown in Figure 3. Including idle (Idle), refurbishing (Ref resh), the pattern register disposition (Mode Register Set), effective (Active), pre-sufficient (Precharge), reads and writes seven conditions. Each condition issues the different operational order to the SDRAM memory.
The SDRAM memory’s operation mainly gives through the following control signal, the RAS# good address selection, the CAS # row address selection, WE # write enable the signal, CS # to select patches or strips of land as worth saving for seed the signal as well as the CKE clock enable the signal. Table 1 has given each instruction combination way. 
Figure 3 SDRAM controller state machine
2. 4 performance analyses
This SDRAM controller module uses the MT48LC2M32B2 simulation module which Micron Corporation provides to carry on the function simulation, the simulation result demonstrated that the design conforms to the standard. The SDRAM controller is on the internal high speed main line each Master the equipment access rate high Slave equipment, its performance quality immediate influence entire SoC operation. This controller reads/writes operation periodicity Lrw is 8, from this may obtain this controller’s read-write cycle for the formula (1), fclk is the basic frequency clock: 
In the SDRAM controller refurbishing periodicity Lref is 4, the refurbishing gap counted tREF to be possible through the pattern register disposition, Table 2 to give 4 kind of values which tREF might suppose, and the basic frequency clock was in the 100MHz situation gap cycle. This then may obtain controller’s refurbishing cycle is: 
When tREF takes the maximum value, may obtain each second biggest user available time is 
When the SDRAM controller carries on 4 character read-write operation, because this controller data line is 64bit, therefore may result in this controller’s biggest data transfer rate DTR (data transfer rate) is type (4): 
And, when basic frequency clock f clk is big enough, type (4) then improper reduces for type (5):
Therefore may obtain, when the basic frequency clock is 100MHz, SDRAM controller’s data transfer rate approximately is 400MB/s; But when the basic frequency clock takes 133MHz, data transfer rate may achieve 522MB/s.
2. 5 design comparisons
The reference [1], provided one to realize the experimental nature SDRAM controller based on the FPGA chip. Compares with this controller, this article design not only has in the performance improves greatly, moreover, because this article design is faces the application, constituted the independent IP nucleus, but this design is the experiment, cannot apply directly in the product, has not constituted the IP nucleus request. Table 3 have given two design performance comparisons. 
2. 6 FPGA confirmations and ASIC realize
This design use dragon core SoC FPGA confirms the platform to carry on the hardware simulation, the hardware simulation platform use FPGA chip is Xilinx Corporation’s XC2V6000, what hardware simulation platform actual use is 128MB in the PC100 modern age the certificate of deposit. The SDRAM controller after FPGA realizes close 50,000 logical gates. Entire SoC designs the work basic frequency which FPGA realizes is 24MHz, FPGA confirms in the platform the SDRAM clock is also 24MHz.
The confirmation indicated: The SDRAM controller works normally in the system. Because the HDL code uses the parametrization the design, ASIC realizes so long as the edition makes the very few revisions. Is different what with FPGA, the ASIC edition has realized the gating clock and the power loss management, in design synchronized FIFO uses Artisan the twin port RAM storehouse production. What the DC synthesis uses is SMIC 0.18μm the craft storehouse, retards the reactionary slogan (back annotation) the gate level simulation’s result indicated that the design meets the anticipated requirement.
3 concluding remark
This design hangs carries on the internal high speed main line, in the concrete structural design aspect, unifies system’s performance analysis and the software and hardware coordination simulation, optimizes various modules the design. And realized IP to be possible to entrust with heavy responsibility the design, namely did not need to make the big modification to the structure, might restructure one to suit the different demand on the piece the SDRAM controller, only needed through the replace interface module to hang meets on other type piece the main line. At the same time, the parametrization design may facilitate the choice realizes the craft. In the design confirmation the IP function meets the anticipated requirements.
