1 introduction
FPGA relies on its convenience nimbly, to be possible to duplicate programs and so on merits, but widely is applied day by day; Dodges the fast memory (Flash Memory) to be high by its integration rate, the cost is low, merits and so on easy to operate, have also obtained the widespread application in the numerous domains. In modern digital circuit design. Needs to preserve the mass data frequently, but the Flash storing velocity is quick, the volume is small, the power loss is low, and low in price, but the online electricity scratches writes, information after power failure will not lose, will therefore become designers’ first choice.
2 M25P80 introductions
Flash is one kind programmable ROM which has the electricity to be possible to clean, may divide into two broad headings: Parallel Flash and serial Flash. The parallel Flash reserves is big, the speed is quick; But the serial Flash reserves is relatively small, but the volume is small, the segment is simple, may reduce the electric circuit area, saves the cost, the two have its good and bad points respectively, may rest on the actual need selection. This article develops the system to the speed request is not very high, but is harsher to the circuit wafer area request, therefore the system design has selected serial FlashM25P80.
M25P80 is section of high speed 8 Mbit serial Flash which the Italian law semiconductor promotes, altogether is composed of 16 parts, each part has 256 pages, each page has 256 bytes. M25P80 has advanced writes the protection mechanism, reads the data the maximum clock rate is 40 MHz. The M25P80 working voltage scope is 2.7 V~3.6 V, has the whole cleaning and the sector cleaning, the nimble page programming instruction and writes the protection function, the data storage at least 20 years, each sector may withstand 100 000 times scratches writes the circulation. The parallel Flash seal usually needs 28 above pins, therefore, the extraneous expense is big, but M25P80 uses the SO8 seal, needs the pin number are few, thus has saved the circuit wafer space, the power, the system noise and the overall cost and so on can reduce large scale, both the economy and is practical.
Figure 1 is the M25P80 pin arrangement, Vcc and Vss respectively be the power source and the place, other 6 pins may direct and the FPGA I/O pin are connected; Writes protection pin W and HOLD hangs up the pin, uses in the data protection and the idle mode low power loss movement, if does not need to be possible to set it for the high level; S is selects patches or strips of land as worth saving for seed the signal, shows the component for the low level watch to select, otherwise works in the readiness for action; Q is the serial data output, the data along outputs the Flash component in clock’s drop; D is the serial data input, including the transmission instruction, the address and loses the person data, the input signal, in clock’s rise saves in the Flash component along the lock. C is the serial clock, provides the clock by FPGA. Because the clock signal speed is high, therefore in the PCB wiring time wants the special attention reduction disturbance, should better use the grounding shield.
3 M25P80 instruction operations
M25P80 altogether has 12 operational orders, all instructions are 8, when the operation will select patches or strips of land as worth saving for seed signal (S) to pull first selects the component lowly, then inputs 8 operational order byte, the serial data after selecting patches or strips of land as worth saving for seed signal S pulls low the first clock’s rise along by the sampling, M25P80 start internal control logic, completes the corresponding operation voluntarily. After the instruction, sometimes must the entry address byte, when the necessity must join reads the byte mutely, after the last operation finished, will select patches or strips of land as worth saving for seed the signal to pull high again. Below introduces several most commonly used instruction operations simply.
3.1 write enables the instruction
When the page programs, before writing the register or the cleaning, must use first writes enables the instruction to establish the register to write enables the position. Or writes on electricity enables the invalid instruction operation, when as well as the page programming, writes the register and cleaning order complete, should write enables the position replacement. Writes enables the instruction the succession to be quite simple, instruction 0000 0110(06h) after selecting patches or strips of land as worth saving for seed the signal pulls low the first clock’s rise along to send in Flash, inputs the top digit first, after the command input completes, pulls immediately selects patches or strips of land as worth saving for seed the signal high, otherwise the Flash protection mechanism thought that is the unwanted signal, but does not carry out this instruction. Writes the invalid instruction with to write enables the instruction to be similar, is only the input instruction-code is 0000 0100(04h).
3.2 read/writes the condition register
The condition register may read at any time, even if also when the page programming, the cleaning or write the register may read the register, may read continuously the condition register. After selecting patches or strips of land as worth saving for seed the signal pulls lowly, sees somebody off 8 to read the register instruction immediately, then Flash the internal register’s value serial output, 8 register contents outputs repeatedly.
Writes the condition register’s sequence of operation: After writing enables the command input completes, pulls high selects patches or strips of land as worth saving for seed the signal, the Flash execution reads enables the instruction establishment register. Then pulls selects patches or strips of land as worth saving for seed the signal lowly, the input writes the register instruction and the data, afterward must pull immediately selects patches or strips of land as worth saving for seed the signal high.
3.3 read the data command
After selecting patches or strips of land as worth saving for seed the signal pulls lowly, first inputs 8 to read the data command, inputs again must read the content 24 first addresses, the address direction data in clock’s drop along the output. After data output, the address increases progressively automatically, and directional next address. Transmission next address direction data, when after the address achieves the highest order, servo-assisted steering first address 000000h, so circulates, reads out in Flash the complete content, until selects patches or strips of land as worth saving for seed the signal to pull high. Reads data command succession as shown in Figure 2.
3.4 page programming instruction
Before page programming, must first input writes enables the instruction, after Flash completes the register establishment, to select patches or strips of land as worth saving for seed the signal to pull lowly, inputs the page programming instruction, follows closely is inputting the programming address and the data-. One time most may input 256 byte data, if the ultra origin only retains 256 bytes which finally inputs. If inputs address low 8 not all are zero, from the input address starts to program, programs to this page finally, starts from this page reference to compile again. After the data loses the human finished, selects patches or strips of land as worth saving for seed the signal to set high. Otherwise does not carry out the page programming instruction. Page programming instruction succession chart as shown in Figure 3.
3.5 cleaning instructions
The cleaning instruction 0 sets at Flash in is 1, divides into the part cleaning and the whole cleans two kind of instructions. The whole cleaning instruction and writes enables the instruction to be similar. Is only the input instruction-code is different, but the part cleaning instruction only needs after the instruction-code the input needs to clean the address then, a time may clean one. Before carrying out these two instructions, needs to carry out first writes enables the instruction.
4 hardware realize
When Flash normal work must strictly according to the Flash sequential control signal. Uses when for the first time Flash certainly must carry on the cleaning operation first, the programming instruction may 1 become 0. When toward Flash in write data, reads in the first data in FPGA ROM, then, in the FPGA interior reads in according to the Flash page programming succession the data in Flash. Selects Altera Corporation’s FPGA, needs the ROM module may transfer in QuartusII directly the great functional module, compiles a control module control to read ROM the time and the address, and sends in the data according to the Flash succession in Flash. Page programming’s module chart as shown in Figure 4. Selects the Flash capacity is big, generally FPGA not such big storage space, therefore the data separable reads in many times. In the FPGA ROM data storage in the .mif document, .mif produces the .mif document directly by Matlab, may also produce in the QuartusII software.
In so long as the Flash data according to reads the succession request to be possible to read in FPGA to carry on the operation smoothly. In the debugging, for proving program’s accuracy, may the data which reads out from Flash through the serial port deliver the computer, module chart as shown in Figure 5. In chart txmit is the serial port transmitting end module chart, it is responsible for the data which will receive according to the RS232C succession form output to the computer. the flash_read module reads the data format according to Flash to send out the control signal, and will deliver the txmit module from the Flash read-out’s data according to the byte pack. After reading the succession confirmation unmistakably, removes the txmit module, will deliver other module participation operation by the Flash read-out’s data.
What needs to pay attention, some instructions after the operation completes, needs to keep period of time Flash to carry on the data processing, if writes register cycle (tw) is 5 ms~15 ms, page programming cycle (tpp) is 1.4 ms~5 ms, part cleaning cycle (tse) is 1 s~3 s, but whole cleaning cycle (tBE) is 10 s~20 s. After these command input had ended, pulls selects patches or strips of land as worth saving for seed the signal enough long time high, may also while carry out these instruction operation to read the internal register value, monitors the above cycle whether to finish. Once examined the instruction execute to finish, then carried out the following operation, like this might the saving of time. If will neglect the Flash process time to have the mistake, caused Flash to be unable the correct executive order.
5 concluding remark
In the digital circuit design needs to use the mass memory unit frequently, the serial Flash volume small, takes the system resources to be few, the segment is simple. Along with microelectronic technology’s rapid development, FPGA the function which displays in the digital circuit design is getting bigger and bigger, widely applies in the system realizes and the function confirmation. Using FPGA positive governing flash connection succession, not only cut down on the special-purpose programmer’s expenditures, moreover facilitates nimbly, is advantageous for the transplant. Uses the hardware to describe the language compilation connection succession, but reuse, probability. The FPGA flexibility and the serial Flash volume small characteristic unifies, has the design to be flexible, the cost is inexpensive, usability strong and so on superiority, and has the important reference value.
