Along with information science’s swift development, the data acquisition and the storage technology widely apply in domains and so on radar, correspondence, telemetering remote sensing. In the high speed data gathering system, transforms after ADC the data needs to save in the memory, carries on corresponding processing again, guaranteed that fast accurate data transmission processing realizes a high speed data gathering key. Is very high as a result of the high speed ADC transfer ratio, but large capacity RAM the relative ADC output speed is slow, maintains the high speed data memory process the reliability, timeliness is a quite thorny question. Regarding data acquisition system’s in large capacity high velocity data storage, the transmission, this article proposed that one kind realizes the high speed data memory and the transmission plan based on FPGA many piece of RAM, and using in the 1GS/s data acquisition system, realized has completed the high speed real-time data memory system’s design by low cost RAM.
Plan choice
The high speed data acquisition speed is guarantees the data acquisition precision the standard, but often in data processing time does not need to carry on by the similar speed, otherwise is too high to hardware’s demand, the cost is also high. This needs to have a data buffer unit, saves effectively the data, acts according to the system requirements to carry on the data processing again.
Usually the constitution high speed buffer’s plan has three kinds. The first kind is FIFO (advanced leaves the way first). The FIFO memory looks like the data pipeline to be the same, the data from a pipeline’s inflow, flows out from another, enters advanced the data flows out first. FIFO has two sets of data lines not to have the address wire, may write the operation in its end, but reads the operation in another end, data in smooth migration, can thus achieve the very high transmission speed and the efficiency, and as a result of has omitted the address wire but is advantageous to the PCB board wiring. The shortcoming is can only the smooth read-write data, is not easy to control nimbly, moreover large capacity high speed FIFO is expensive.
The second kind is the pair of mouth RAM way. Double mouth RAM has two sets of independent data, the address and the control bus, thus may from two ports at the same time the read-write, but does not disturb mutually, and may read in the sampled data from a port, but reads out by the controller from another port. Double mouth RAM can also achieve the very high transmission speed, and has the random access merit, the shortcoming is the large capacity high speed pair of mouth RAM price is very expensive.
The third kind is the high speed SRAM cut way. High speed SRAM only then a set of data, the address and the control bus, may receive on separately a/D switch and the controller through the three states of matter cushion gate. When A/D sampling, SRAM cuts A/D switch one side from the three states of matter gate, causes the sampled data to read in which. After a/D sampling had ended, SRAM cuts controller one side from the three states of matter gate to carry on the read-write again. This way’s merit is SRAM may the random access, simultaneously large capacity high speed SRAM has the ready-made product to be possible to supply the choice.
From reduces in the cost to consider that selects the third method to realize the large capacity data storage function. Unifies the 1GS/s data acquisition system’s request, the memory depth is 4MB. Chooses ISSI Corporation’s static RAM, constitutes the 4MB test data memory by 8 piece of IS61LV25616, system structure as shown in Figure 1.
Figure 1 data storage functional block diagram
Data storage design
* data flow control
ADC is the double channel 500MS/s transfer ratio, the 8bit vertical resolution, transforms the data the output is in each channel I, Q two directions the differential motion output, under the differential motion clock 500MHz actuation, may realize the 1GS/s real-time sampling rate, outputs 4 group transformation data stream output by ADC respectively is 250MS/s. But IS61LV256 the series RAM speed rank is 10ns or 12ns, such data must carries on the buffer after FPGA, only then may once more store RAM.
IS61LV25616 the series RAM chip has 16 bit data lines, 18 bit address width, meanwhile includes the data CS control signals and so on to read RD, to write WR and to select patches or strips of land as worth saving for seed. Parallel connects on FPGA 8 piece of RAM, composes data acquisition the memory cell.
Will output AI[8…0], AQ[8…0], BI[8…0], BQ[8…0] from ADC, each group signal is the LVDS output, altogether 32 are a group transforms data DATA[31…0], the speed is 250MS/s, must drop to this speed in the FPGA interior the RAM acceptable scope. Selects CycloneII series FPGA, its internal clock may work in 402.5MHz, supports the single end and the high speed differential motion standard I/O connection, definitely may receive regarding the 250MS/s data stream. Trigger takes the cushion using FPGA the internal D, after passing through 4 levels of cushions, obtains DBO[127…0] separately, such data speed reduces to 62.5MS/s. After the process cushion’s data already in selected RAM accepts in the speed rank, will obtain 128 data to take 8 piece of RAM the data lines, has completed the data stream control. Data buffering’s principle as shown in Figure 2.
Figure 2 data buffering design
* address generator design
When each time read-write data, must provide the data the storage location, takes the clock counting signal by the read-write signal, produces the address signal in turn, NWE is RAM writes the data signal, NOE is the reading according to what is believed number, the two are the low level are effective, choose AB[17…0] to take the RAM group the address signal. CNTEN is the address counter enables the signal, decided by the read/write data’s depth, when has not completed the data which the read/reads, CNTEN=0, this time allows to read/writes the operation to continue to carry out; When reads/writes the operation completes, the corresponding address signal the CNTEN establishment is 1, then stop address counting. Address generator’s principle as shown in Figure 3.
Figure 3 address generator design
* read-write data design
After designing the good gathering data the address has the unit, is coordinates the succession to carry on the read-write operation.
Figure 4 is RAM reads the operation succession chart, may see from the chart, when after assigning treats the operation the address, the establishment chip enables signal OE and selects patches or strips of land as worth saving for seed enables signal CE to be effective, then reads out in the corresponding address from the data line the data.
Figure 4 RAM reads the data succession chart
Is quite simple regarding the monolithic RAM operation, but must read in the data order in 8 piece of RAM, requests after previous piece of RAM to write the operation completes, the system can establishment next wait the operation RAM to be effective, 128 data lines correspond 8 piece of RAM separately the data lines, because the address wire and the read-write enable the line public, then needs to establish each RAM separately selecting patches or strips of land as worth saving for seed, which RAM distinguishes the current operation aims. Selects patches or strips of land as worth saving for seed the signal to be possible to produce by the decoder. Reads when the operation establishes corresponding RAM to select patches or strips of land as worth saving for seed effectively, then reads out the data which saves, when carries on writes the operation, then may establish all RAM to select patches or strips of land as worth saving for seed effectively, will gather at the same time the data parallel reads in 8 piece of RAM. According to these descriptions, selects patches or strips of land as worth saving for seed the signal design as shown in Figure 5. NIOMD is the operation status signal, explained that the current operation is reads the condition perhaps writes the condition, reads in the data situation the establishment is 1, selects patches or strips of land as worth saving for seed the signal distinction to be effective, writes in the data situation the establishment is 0, all RAM is at selects patches or strips of land as worth saving for seed under the effective condition, may simultaneously the write data. Such design is also to coordinate system’s demand, generally, read the data the speed to be opposite at writes the data to want quickly some.
Figure 5 RAM selects patches or strips of land as worth saving for seed enables the signal design
Simulation confirmation
After the above design proposal conformity, coordinates other control signal the design, has completed the data acquisition system data storage function design. Carries on the profile simulation in the QuartusII software to above design, may see establishes the SET value and the corresponding state control signal, in the VDB end may defer to the data which CS the instruction in the corresponding RAM chip the smooth read-out stores in advance. According to the condition register establishment which in the chart shows, the read depth establishment register establishes as minimum value SET[4…1]=000, namely read-only each piece of RAM first stored datum, then address generator’s maximum is 8, may see from the chart, when the address generator value of exports increases to 8, the WE jump is the high level, RAM reads enables invalid. As a result of AB[3]=1, causes CNTEN=1, the address generator counting clock to enable invalid, the counter stop counting, completes a round data the read operation. Reads data simulation confirmation result as shown in Figure 6.
Figure 6 reads the data simulation confirmation
In Figure 6, regarding current data line’s in burst DB=0010,0011,1010,1110,1101,0011,1001,0111, selects patches or strips of land as worth saving for seed the signal CS low level to be effective, when CS=11011111, in being appointed to fill a vacancy according to the order from the low position to top digit computation’s 6th piece of RAM, this time corresponds the data which reads out on VDB to be the DB 6th data value, is 1010. Obtains the confirmation from the profile policy chart.
Conclusion
Using the FPGA internal resources, design the nimble logical control, completes the high speed large capacity data acquisition the memory and the transmission design, the design proposal which this article proposed may in select the low cost, the simplicity of operator in the static RAM group’s situation, realizes the real-time large capacity data storage demand one design method, and has carried on the simulation confirmation in the EDA software, applies successfully in the 1GS/s data acquisition module.
