The abstract radar receiver turns the radar echo signal the intermediate frequency signal, the digital signal processing system to the intermediate frequency signal sampling and processing. This article introduces one kind based on A/D and the DSP intermediate frequency signal gathering technology; Gives data acquisition system’s principle and the diagram, and carries on the analysis to A/D and the DSP interface circuit. Takes between both’s connection effect with FIFO to be very good; DSP carries on the control through CPLD to the sampling succession, may strengthen system’s flexibility.
Key word A/D the DSP high speed data gather FIFO
The intermediate frequency signal divides into and misses two groups, high speed A/D and the DSP composition’s data acquisition system must carry on gathering separately to these two groups signals. Regarding two group data acquisition electric circuit, A/D and the DSP connection connection is the same. At the same time two A/D with the road and the difference road signal sampling, and will send in two FIFO separately; DSP time sharing reads out gathering from two FIFO the data, completes the data gathering.
1 data acquisition system composition and principle
The data acquisition system by A/D, FIFO, CPLD as well as the digital signal processing board is composed, Figure 1 is the gathering system composes the diagram.
In the system, simulates the intermediate frequency signal with the road and the difference road intermediate frequency signal, the simulated signal will turn the digital signal after a/D chip, after the FIFO chip, the data which will gather sends in the digital signal processing board again. In the digital signal processing board’s processor is DSP. DSP data line and 2 piece of FIFO data line connection, simultaneously also with the CPLD connection, address wire and CPLD connection. 2 piece of FIFO chip’s read-write control logic carries on the control by 1 CPLD. CPLD and superior machine data line, address wire connection, digital signal processing board through CPLD and superior machine correspondence.
2 chip characteristics and choice
2.1 AD6644 high speed modulus switch
AD6644 is one kind of one piece type high speed, the high performance 14 mold/number switch, the content sampling maintains the electric circuit and the datum source. AD6644 provides compatible 3.3V the CMOS level output; The sampling speed is highest may reach 65Msps, generally the sampling speed is 40 Msps; The signal-to-noise ratio typical value is 74 dB, does not have stray dynamirange SFDR is 100 dB; The power loss is 1.3W, the input simulation band width may reach 250 MHz, the temperature range for - 25℃~ 85℃.
AD6644 uses the third-level subsegment-like transformation structure, both guaranteed the precision and to reduce the power loss, its function diagram as shown in Figure 2. Its simulated signal input mode is the difference structure, each input’s voltage take 2.4V as a center, high and low scope in 0.55V. As a result of two input phase differences 180°, therefore AD6644 traces plans the input signal a biggest peak peak value is 2.2V. May see by Figure 2, difference analogue input end first after the cushion enters first sampling retainer (THl). When codes the clock for high, THl enters maintains a condition. In TH1 maintains the value takes thick 5 ADCl the input. The ADCl digital output actuates 5 figure/mold switch DACl. The DACl request has 14 precisions which adjusts through the laser. The detention simulated signal and the DACl output cancellation, produces the first surplus signal, and gives sampling retainer TH3. The sampling retainer TH2 function is the detention, to compensate ADCl the digital time delay to provide the simulation time delay, caused to send in TH3 two groups signals also to arrive.
The first surplus signal enters the 2nd transformation stage which and channel TH4 is composed of 5 ADC2,5 position DAC2. 2nd DAC requests to have the adjustment 10 precisions. The TH5 input is through with is retarded by the DAC2 output by TH4 the 2nd surplus signal which the 1st surplus signal obtains to cancel, TH4 and TH2 behave identically. TH5 actuates final 6 ADC3. ADCl, ADC2, the ADC3 digital output sum total and the digital error adjust logic to have the final output data, the result are 14 two’s complement code parallel data together.
2.2 TMS320C6713
This module’s DSP chip selects TI Corporation’s floating point digital signal processor TMS320C6713. In TMS320C6713 has 8 parallel processing units, divides into the same two groups. Its architecture uses the ultra long instruction word (VLIW, Very Long Instruction Word) the structure, single instruction long 32, 8 instructions compose an instruction package, altogether word length for 8×32=256 position. The chip internal has established the special instruction assignment module, may each 256 be supposed the instruction package simultaneously assigns to 8 processing units, and also moves by 8 units. The chip highest clock rate reaches 225MHz, its biggest handling ability may achieve 1800MIPS. The TMS320C6713 above characteristic, had guaranteed rear end signal processing’s timeliness, can satisfy this system’s performance requirement.
2.3 FIFO memory IDT72V253
The FIFO memory permission data reads in by the different speed and reads out, IDl72V253 is one kind of high speed 4096 character ×18 position FIFO component, as shown in Figure 3. Its upper frequency may reach 166MHz, the data write data reading duration is 10ns. When locks into when the number of words surpasses 4096, the memory enters the full condition. The FIFO condition may the pass time passage period and status byte - - full (FF/IR), spatial (EF/OR), half-full (HF), PAE and PAF obtains. When the memory is full, the FF/IR output is the low level; When the memory is a free time, the EF/OR output is the low level. When FIFO has many in 2048 character contents, HF output for high. PAE and the PAF status byte is the programmable status byte. When writes enables to carry the WEN level changes is low, treats sends in FIFO the data under the WCLK clock’s synchronization to send in FIFO, when the first character is read, the EF/OR pin’s level becomes the high level; When sends in the data surpasses (n 1) (n is the PAE bias value) a word-time, programmable status byte PAE becomes the high level; When has (D/2) l(2049) character reads, the HF pin level changes low; Continues along with the data to read, will cause the PAF pin level will change low. If does not have the data read-out, when has (D-m)(4096-m) character reads, the PAF pin level changes low. When the FIFO data writes all over (regarding IDT72V253, reads in 4096
The character), the FF/IR shift is the low level, prevents the data further read-. When FIFO writes all over, first will read the operation to cause the FF position level will change high, afterward reads the operation to cause HF and the PAF pin level will change high. When inside FIFO only then n word-time, the PAE pin level changes low; When last character from the FIFO read-out, the EF pin level changes low, the impediment further reads the operation.
3 high speed A/D switches and DSP connection design
3.1 connection designs
AD6644 is 14 modulus switches, IDT72V253 is 18 FIFO, TMS320C6713 DSP data bus is 32, therefore IDT72V253 and TMS320C6713 only need meet low 14 DO~D13. Because FIFO enters first leaves the special structure first, in the system does not need any address wire the participation, simplified the electric circuit greatly. A/D sampling obtained data must real-time send in FIFO, therefore both write the clock rate to be the same, and AD6644 and the IDT72V253 smallest clock input is 10ns, operates the unification to be convenient. CPLD selects Xilinx Corporation’s xc95144×1-tql44, realizes 42 input AND gates with it, in TMS320C6713 general cushion serial port (Mcbsp) DX, the FSX disposition for general outlet (GPIO), carries on the control to this 42 input AND gate’s make-and-break, thus writes the clock to a/D switch and FIFO to carry on the control. Because exterior FIFO is taking the TMS320C6713 CEO space, therefore reads the signal the logical relation is: After R=CEO ARE, TMS320C6713 CEO and ARE “and”, is connected with IDT72V253 RCLK, is FIFO provides reads the clock (CE0 and ARE “and” completes by xc95144xl-tql44). TMS320C6713 CLKX and IDT72V253 reset signal PRS use to reposition FIFO connected. Connection diagram as shown in Figure 4.
3.2 succession designs
“And” the gate separately writes the clock through two to a/D switch and FIFO to carry on the control, because AD6644 starts from the analog input to this transformation data to appear on the outlet needs 4 clock cycles, and in high velocity sampling time the wire time delay effect will be obvious, if a/D switch and the FIFO clock in the same place, very possible excessively many to pick continually the invalid data. After separating the control, through the software time delay, may conveniently separately carries on the control to a/D switch and the FIFO clock, debugs quite conveniently, tries hard to pick the invalid data the figure to reduce to lowly. AD6644 work succession as shown in Figure 5, IDT72V253 writes succession as shown in Figure 6.
When sampling, causes DX and the FSX output through the procedure is 1. After this time sampling pulse and DX, FSX “and”, is sent in AD6644 separately clock input ENCODE and IDT72V253 writes the clock input WCLK, A/D switch to start to work, and will transform the data to deliver unceasingly to own outlet D0~D7. When writes enables WEN is low, on a/D switch outlet’s data in the WCLK rise along in turn is read in FIFO. A/D switch and FIFO come one time every time the pulse, then completes an a/d conversion and stores the data order FIF. Causes IDT72V253 LD is low, FSEL0 is when high, FSEL1 is high, after IDT72V253 undergoes the main replacement, drift rate n, m are the default value 63, after each radar echo impulse sampling 63 spots, the memory symbolized nearly completely PAF outputs the low level (in not to 63:00 outputs high level). Receives TMS320C6713 this indication on external interrupt INT0, uses its change from high to low to have the interrupt, indicated that a group of data acquisition completes.
In the interrupt, DSP first rapidly closes the sampling pulse signal (to cause DX and the FSX output is 0), stops a/D switch and the FIFO work. After TMS320C6713 CE0 and ARE “and”, reads with FIFO inputs RCLK to meet in the same place, DSP carries out time I/O to read the operation every time, R=CE0 ARE then sends out a pulse to RCLK, reads FIFO enables PEN to set to lowly, simultaneously carries out 63 time I/O to read the operation continuously, the data then in turn sends in TMS320C6713 from IDT72V253, the entire data acquisition work completes in light of this. Before carrying on the second data gathering, should better reposition first IDT72V253, TMS320C6713 the general cushion serial port’s CLKX disposition is the general outlet, inputs one for the IDT72V253 PRS pin is not smaller than the 10ns low pulse, namely outputs a low pulse in the DSP CLKX pin. This may guarantee fully FIFO reads, writes indicator’s stability.
3.3 software designs
Software design including CPLD and DSP two parts. The CPLD procedure with the VHDL language compilation, realizes the simple logical conversion function, the programming is quite simple. In the DSP programming has several committed steps: The external interrupt enables, the clock to send in a/D switch and FIFO, the waiting interrupt, stops a/D switch and FIFO, the gathering data, repositions FIFO. Entire software flow as shown in Figure 7.
4 conclusions
Supposes the juice through the reality to indicate that in the DSP high speed data gathering system, uses the FIFO component to take between a/D switch and the DSP bridge, may establish FIFO according to the concrete need to symbolize one by one nimbly, enables it to have the very strong exterior connection ability; And is very easy through the software to adjust a/D switch, FIFO and the DSP operation succession, strengthened the operation flexibility, played the very good data buffering role, had guaranteed data acquisition’s security was reliable. The system hardware has the structure to be simple, perform reliably characteristic; The software has the control to be nimble, merits and so on program debugging convenience.
