The high speed data save in the high speed data gathering memory system, the data storage is a key technologies. The procedure usually is stores the data in the mass memory unit, after gathering had ended, carries on the data processing and the preservation again. This method. The acquisition time storage capacity’s limit, possibly is continually unable in many situations to satisfy the request; But storage capacity’s increase, its price doubled and re-doubled will also grow. Therefore, from aspect overall evaluations and so on storage capacity, read-write speed and unit cost, uses the high speed hard disk immediate data memory has the superiority very much.
Speaking of the hard disk, in continues in the high speed data memory, whether is the key it continues the data transfer rate (sustained transfer rate) to satisfy requests. At present, 15000r/min minicomputer system connection SCSI (Small Computer System Interface) the hard disk, the main line data transfer rate is 80~320MB/s, continues the data transfer rate to be bigger than 40MB/s. But PC machine universal disposition IDE hard disk, although its main line data transfer rate may achieve 33~100MB/s, but continues the data transfer rate only then about 15MB/s, the performance is lower than the SCSI hard disk.
This article has designed one kind of special-purpose high speed hard disk storage device, it is separated from the microcomputer platform real-time to send in the high speed data the SCSI hard disk, saves the speed to be possible continually to reach 35MB/s (to use the ST336752LW hard disk which Seagate Corporation produces).
1 SCSI main line and hard disk
SCSI is between the computer which and the peripheral device interface standard the American ANSI9.2 Committee defines, at first is by the floppy disk storage device primarily, not only but as a result of characteristics and so on its flexibility, equipment independence, causes it, in the magnetic tape equipment, the printing device, the compact disc actuate peripheral devices and so on equipment to obtain the universal application, also in many I/O equipment and the computer network, domains and so on computer industrial control develops unceasingly. Along with the peripheral device speed’s unceasing enhancement, the SCSI performance enhances one time nearly every five years, at present Ultra320 the SCSI main line data transfer rate may reach 320MB/s.
SCSI is the equipment irrelevant input/output bus, may hang meets reaches 8 above equipment. Regarding SCSI main line’s on equipment, if is duty trigger, is called the starting outfit; If is the duty performer, is called the goal equipment. Usually the starting outfit chooses a goal equipment first, subsequently by the goal equipment decided that continues the control bus or releases the main line, until completes the task. This article special-purpose high speed hard disk storage device uses the list to start, the simple target structure.
The SCSI hard disk when marks the hard disk sector has used the linear concept, namely hard disk only then the smooth 1st sector, the 2nd sector…The n sector, does not look like the IDE hard disk “the cylinder/magnetic head/sector” the three dimensional form. This kind of linear arrangement way visit time delay is smallest, may speed up the hard disk access speed, especially when continues the large capacity data storage, appears the superiority is obvious. At present, the operating system interior also uses the linear serial number the sector, its goal speeds up the medium access speed, enlarges the medium visit capacity.
In summary, this special-purpose high speed hard disk storage device uses the SCSI main line data transfer rate to be not only high, moreover when need may increase in equipment’s hard disk quantity to expand saves the spatial quantity, even may the hard disk replace for other SCSI storage device.
2 system structure designs to realize the SCSI agreement and the hard disk save, generally needs to have the microprocessor, the DMA controller, SCSI hardware supports and the corresponding software control module and so on agreement controller, data buffer storage.
· the microprocessor uses for in the control device various parts’ work, realizes equipment’s specific function. This special-purpose high speed hard disk storage device realizes the data to continue to save high speed, the request processing data’s speed is high. Usually these need to transmit and process the mass data the equipment to select digital signal processor DSP to take the microprocessor. At the same time, in the SCSI agreement many complex control functions also need this microprocessor to realize.
· the transmission mass data mostly will use the direct memory to visit DMA (Direct Memory Access) the way, will therefore need the independent DMA controller or selects the built-in DMA controller’s microprocessor. And raises the speed stemming from the simplified circuit the consideration, this equipment used complex programmable logical component CPLD to construct an independent DMA controller.
· must realize the SCSI agreement to need to have the SCSI agreement controller. In DSP usually does not gather the SCSI agreement controller, therefore in the ordinary circumstances, needs to choose the general SCSI agreement controller, is auxiliary DSP to realize the SCSI agreement and the correspondence.
· in equipment’s input connection part, needs to have the data buffer unit. The ordinary memory while which reads in cannot read; Uses pair of mouth stochastic memory RAM, although may solve the concurrent visit problem, but its essential both sides address decoding is also the noticeable question. Regarding the pure data storage equipment, does not need to do pretreatment work and so on compression, signal analysis to the data, the buffer unit is equal advanced to the structure leaves (First In First Out, FIFO) the first formation, arrives the first data is saved first. Therefore uses the special-purpose FIFO chip, may remove the complex buffer storage decoding circuit, big simplified system design. Moreover, uses the special-purpose FIFO chip, the entire equipment looks like from the exterior data interface, is one writes discontented FIFO, also simplified greatly to the equipment data interface operation.
Special-purpose high speed hard disk storage device’s diagram as shown in Figure 1. Figure 1 various squares expressed that a basic module, the parenthesis Chinese character expressed realizes specifically the component, left side of the dashed line the part does not belong to the equipment module.
In this high speed hard disk storage device design selected the TMS320F206, SCSI agreement controller which to the processor TI Corporation produced to select the FAS368M, DMA controller which and other periphery logical conversion electric circuit Qlogic Corporation produced has selected CPLD which ALTERA Corporation produced component EPM7064.
TMS320C206 is CPLD which TI Corporation produces component EPM7064.
TMS320C206 is in the TMS320 series monolithic digital signal processor’s one kind of low price which, the high performance fixed-point DSP chip TI Corporation produces. This chip power loss is low, handling ability, the instruction cycle most is short is 25ns, the operational capability reaches 40MIPS, internal has the 32KB twinkle memory and 4.5KB RAM, is uses one of most early twinkle memory’s DSP chips. Because the twinkle memory has ROM is more nimble than, the characteristic which is cheaper than RAM, therefore used TMS320F206 not only to reduce the cost, to reduce the volume, simultaneously the system upgrade quite to be also convenient.
FAS368M is with SCSI-3 the standard completely compatible SCSI agreement controller, it supports the starting outfit and the goal equipment two kind of patterns, the synchro data transmission speed is 40MB/s. Moreover, the FAS368M support is biggest 50 MB/s the fast DMA data biographies. Because uses the separation the microprocessor main line and the DMA bus structure, can therefore have the response by the high speed, but will not create the bottleneck effect.
3 hardware circuits and between functional description TMS320F206, FAS368M, EMP7064 and IDT7208 concrete connection line as shown in Figure 2.
3.1 FAS368M signals and internal register explanation
Figure 2 FAS368M main signal and the control logic is as follows:
· ACK, ATM, BSY, CD, IO, MSG, REQ, RST, SD0~15, SDP0~1, SEL and the difference signal, is FAS368M and the SCSI main line’s connection signal.
· The CS signal is the read-write FAS368M interior register selects patches or strips of land as worth saving for seed the signal.
· RD, WR are the FAS368M interior register’s read-write signals.
· The FAS368M TNI end corresponds TMS320F206 external interrupt INT1, when its is effective, indicated that had the mistake to have (for example verification to make a mistake), an event to need to serve (for example FAS368M to select as goal equipment) or has finished some service (for example the DMA conclusion).
· DREQ, FAS368M causes DREQ (EPM7064) to send out the DMA transmission request effectively to the DMA controller.
· DACK, EPM7064 to FAS368M DMA request signal DREQ response.
· The DBWR, DMA data writes a letter the number. When DREQ and the DACK signal is effective, EPM7064 controls this signal and the buffer storage IDT7208 RD signal, realizes the data from IDT7208 to the FAS368M synchronized speedy transmission.
FAS368M realizes all SCSI physics agreement under the TMS320F206 control, including arbitration, choice, news, order, data, condition and so on various stages stipulation signal level transformation and so on. TMS320F206 the control is through realizes in the equipment to FAS368M to its register’s read-write.
· the instruction register (Command Register), TMS320F206 through reads in the corresponding instruction to the instruction register, realizes such as the FAS368M initialization and the replacement, the SCSI total line segment allots the replacement, the SCSI main line various stages migration and so on to possess in view of FAS358M and the SCSI main line’s control.
· The FIFO register (FIFO Register) is a 16 character FIFO register, between the hard disk and the FAS368M data must pass the FIFO register. It has two aspect uses: When FAS368M through the SCSI main line to hard disk transmission data and order, may the first data which and the order must transmit places the FIFO register, and so on SCSI main lines are idle, and will obtain the main line domination later again to start to transmit; On the other hand, from SCSI bus transfer to FAS368M data, may also, because TMS320F206 or the DMA controller is busy at stopping, the data delivers the FIFO register to vacate the SCSI main line first, and so on TMS320F206 or DMA controller idle again from FIFO register read data.
· the transmission counter register (Transfer Count Register) is one reduces the counter, it usually uses for to preserve a DMA order to transmit the data byte count.
· the interrupt register (Interrupt Register), FAS368M all information interrupt the way informs TMS320F206. TMS320F206 checks the accumulator through the read interrupt register and other conditions to judge FAS368 to have the interrupt reason, the decision next step the operation, thus realizes FAS368M to the TMS320F206 correspondence.
3.2 EPM7064 interior logic and function
In equipment’s DMA controller realizes by CPLD component EPM7064, this mainly has the following several aspect consideration:
(1) the equipment interface buffer storage uses special-purpose FIFO chip IDT7208, its data bus may with the FAS368M DMA data bus direct connection, not need the complex buffer storage address decoding electric circuit. Therefore, the DMA controller does not need the data and the address bus, the hardware segment may reduce greatly. But coordinates FAS368M the DMA data transmission the succession, the DMA controller only need, in DMA transmission request signal DREQ is effective, and IDT7208 spatial signal EF is invalid time, causes DMA to transmit response signal DACK to be effective, afterward produces synchronized IDT7208 under the clock signal CLK actuation to read signal RD and DMA continuously writes a letter number DBWR, realizes from IDT7208 to the FAS368M DMA transmission; Otherwise, then causes DMA to transmit response signal DACK to be invalid, afterward stops producing IDT7208 to read signal RD and DMA writes a letter number DBWR, interrupts from IDT7208 to the FAS368M DMA transmission. These sequential logic definitely may use a piece of small CPLD component to realize, therefore selected EPM7064 to design this DMA controller.
(2) the FAS368M support reaches as high as 50MB/s the fast DMA transmission. The special-purpose DMA controller chip generally is competent with difficulty, moreover the special-purpose DMA controller and the FAS368M connection needs certain logical conversion electric circuit, the periphery hardware segment are also many. At the same time, it must be together coordinated under the TMS320F206 control with FAS368M the work to be able to realize the DMA transmission, also increased software’s complex degree.
(3) uses EPM7064 besides to realize the DMA controller’s function, but may also entire equipment modules and so on electric circuit’s some decoding, logical conversion one and designs, reduced equipment’s volume in the very big procedure, simultaneously also has provided conveniently for equipment’s improvement and the promotion.
In hardware design’s foundation, the DSP microprocessor also needs a software module to be responsible for the related hardware control and coordinated, realizes the SCSI agreement, hard disk’s control and the DMA transmission finally and so on. To the DSP microprocessor’s programming, needs to grasp the SCSI-3 protocol standard and the FAS368M order collection completely, the work load is quite big, simultaneously the procedure fit and unfit quality also relate system’s storing velocity and the reliability.
