Abstract: According to the design requirements, uses in the Matlab signal processing toolbox’s filter, may design very conveniently meets the application requirement not after the quantification IIR filter, and further uses the VHDL language to describe, after translation, function simulation, synthesis and succession simulation might realize on FPGA. This design extension is good, in actual use, but revises the periphery parameter to change filter’s frequency response suitably, performs according to the different request on different scale’s FPGA to realize.
Key word: IIR digit filter, cascade structure, FPGA
Abstract:The introduction of this paper is in height of the method of the high-step IIR digital adopting cascade structure of wave filter in realizing on FPGA. the wave filter of Matlab design in signal handling tool case are used to design the IIR wave filter that does not be quantified in accordance with application requirement very conveniently, and it is further described with VHDL language, through compiling, function emulatation, synthesis and can be realized on FPGA after sequential emulatation. This design development is good, and in actual use, the proper modificaion of peripheral parameter frequency that changes wave filter respondence can be realized according to different requirements on the FPGA of different scales.
Keywords: IIR digital wave filter; cascade structure; FPGA
1 introduction
In recent years as a result of Semiconductor Technology, computer technology mature and rapidly expand, causes technical and the life close union, particularly digital signal processing’s progressing by leaps and bounds, as well as many modules can digitize and the integration, has provided small, multi-purpose, the low cost and the low power consumption characteristic. Because the digital signal on congenital surpasses the simulated signal, therefore the digital signal compares the simulated signal to the noise immunity to come far well, enables the digital signal the long time preservation or the long distance transmission, and is not quite easy to have the distorted phenomenon. The digital signal processing (Digital Signal Processing DSP) was corresponding and the information system, the signal and the information system, the automatic control, the radar, the military, the aerospace, the medical service and the domestic electric appliances and so on numerous domains obtained the widespread application. This design is based on the digital signal processing foundation, realizes the IIR digital filtering, regarding the gathering signal precision’s enhancement, has profits from the significance.
2 hardware system introduction
2.1 system diagrams
System hardware diagram as shown in Figure 2.1. Mainly transforms, FPGA, the memory and D/A by A/D transforms four parts to be composed.
2.2 part of chip introductions
An electric circuit’s performance and primary device’s choice is close related, below from the control chip, the memory, a/D transformation and D/A will transform four aspects to introduce the system hardware design.
The digital signal processing chip, we select use Xilinx Corporation’s XC2S50 the model the FPGA chip. Carries on the data acquisition with FPGA to save has the following merit: (1) FPGA adopts has how many data conversion chip with how many control unit module strategy, the functional control module and the data conversion chip is 11 corresponding relations, has guaranteed the data acquisition complete parallelism on the hardware; (2) in the XC2S50 chip has the RAM block, may design is the data buffering, facilitates solution data stream blocking the question; (3) the FPGA chip read-write speed is high, will gather and the storing velocity on will not have any problem; (4) the FPGA design uses the online programming the way to carry on, revision and debugging quite quickly, convenient; (5) the FPGA peripheral circuit besides disposes the chip together, no longer needs other any periphery component, the integration rate is high, reliable.
Regarding A/D and the D/A transformation chip, we select the high accuracy 16 transformation chip ADS8402 and MAX5631, is advantageous measures the data in the enhancement the precision.
2.3 hardware work process
The sensor gathering simulated signal, will later transform after the ADS8402 chip into the digital signal, will input in the FPGA chip the digital signal, the FPGA chip will use the IIR digital filtering algorithm to carry on processing to the input signal, after will process the signal may carry on the transmission at the same time through the digital interface, on the other hand may pass through the AD transformation to simulate the quantity the form output, through the around output and input signal’s contrast, we may the direct-viewing analysis filter effect.
3 IIR digit filter’s principle and design
The digital filter realize digital filtering’s core component, divides into 2 broad headings according to the type: Infinite impulse response IIR and limited impulse response FIR digit filter. The IIR digit filter have the broad application prospect in many domains, compares with the FIR digit filter, it may use the low exponent number to obtain the high selectivity, requests the step are few with the memory cell, and the cost is low, the signal delay is small, meanwhile may use the analog filter design achievement, the design work load is relatively small.
3.1 IIR digit filter’s structure
The higher order IIR filter may through the transfer function, the expression be:
(3.1-1)
Because the higher order IIR filter may use certain second-order network cascade to constitute. Regarding each second-order fundamental segment,
It may use the transposition direct II structure to realize, as shown in Figure 3.1.
Figure 3.1 standard second-order part transformation
3.2 filter coefficient computation
This system’s design target is: The simulated signal sampling frequency is 2MHZ, every week time least sampling 20 o’clock, namely simulated signal’s pass band edge frequency is fp = 100KHZ, stop-band edge frequency fs = 1MHz, the pass band fluctuates RP not to be bigger than 0.1dB (pass band error not to be bigger than 5%), the stop-band weakens AS is not smaller than 32dB.
This system function H(z) computation uses in the MATLAB software the digital signal processing toolbox to be quite convenient, the including two ready-made functions may use: ellipord (Fp/π, Fs/π, Rp, As) the function uses for to calculate digital ellipse filter’s order N and 3dB cut-off frequency Fn, but ellip (N, Rp, As, Fn) the function may obtain direct ellipse IIR filter’s each coefficient. Carries on the computation using the MATLAB software, may result in: b = (0.0271 -0.0724 0.0984 -0.0724 0.0271), a = (1.0000 -3.3553 4.3439 -2.5578 0.5771).
Through transfers the system function which above two functional calculus obtains:
(3.2-1)
The above formula is the direct structure, it the multiplier which and the detention unit realizes needs is relatively many, moreover molecular and the denominator coefficient difference is big, needs the many binary digits to be able to realize the corresponding accuracy requirement. If uses second-order ranks the association to realize, as soon as comes each fundamental segment zero spot, the extreme to be possible to make the adjustment alone very conveniently, two come to be possible to reduce to the binary number figure request. Below gave a direct structure to transfer the cascade structure 
the document, namely used [b0, b, a]=dir2cas(b, a), might result in b0 = 0.0271. Carries on the possible arrangement after this coefficient may result in the type (3.2-2):
In order to cause the design to be simple as well as the resources full use, we should carry on the further quantification to the coefficient, transforms the coefficient by the decimal as the integer, according to needs mainly to consider that the quantification precision and the system resources two aspects, simultaneously expands after the second-order network’s coefficient N time, take the new coefficient, then output network’s coefficient will reduce N time again, and carries on the expression with the binary number, the following table 3.1 show:
Table 3.1 filter coefficient expansion
|
Coefficient |
a0 |
a1 |
a2 |
b0 |
b1 |
|
|
IIR1 |
Original data |
0.11 |
0.1041 |
0.11 |
1.58 |
0.6469 |
|
After expanding 1024 coefficients |
113 |
107 |
113 |
1618 |
662 |
|
|
IIR2 |
Original coefficient |
0.2464 |
0.426 |
0.2464 |
1.7753 |
0.892 |
|
After expanding 1024 coefficients |
252 |
436 |
252 |
1818 |
913 |
|
Expands after the coefficient the system function cascade expression is:
(3.2-3)
The following to use the VHDL language to compile the filter cascade structure the partial source programs
The first level rides accumulator’s source program to be as follows:
entity mac is
Port (clk:in std_logic;
x0:in bits8;
x1:in bits8;
x2:in bits8;
y0:in bits8;
y1:in bits8;
y2:out bits8
);
end mac;
architecture flex of mac is
begin
process
begin
wait until clk=’1′;
y2<=(113*x2-107*x1 113*x0 1618*y1-662*y0)/1024;
end process;
end flex;
And the second level while accumulator’s source program with the first level basic similar, the first level outputs while the accumulator for the second level while an accumulator’s input, other inputs for the first level of output after register’s output, or for the signal which feeds back, the input clock and the reset signal are the same, the second level rides accumulator’s output, also for total output.
4 concluding remark
This proof procedure’s input signal is a sine 100HZ signal, on a signal output stable add-on high pulse 200, a low pulse 50, when original state, the signal value initialization is 0, when X signal undergoes the continual input, the signal stabilizes gradually, and inputs the IIR filter’s difference equation to carry on the filter, the interfering impulse will filter out, outputs the 100HZ stable sinusoidal signal, this signal’s pass band weaken is 0.09 dB, the stop-band weaken is 32.7 dB, satisfies the design requirements.
Reference
[1]. Luo Pengfei, Yang Shihai, Zhu national wealth translation. [UK] EmmanuelC.I feachor, BarrieW Jervis. digital signal processing practice method. [M] Beijing: Electronics industry publishing house .2004; 5:82~84
[2] snow Ni, to east. Based on FPGA fourth-order IIR digit filter, Chongqing Normal school information technology department. 4:71~75
no matter what [3] the brave peak, Zhuang Xinmin .VHDL and the hardware realize intensively, Defense industry Publishing house .2005; 5:158~159
[4] Wang Shi one. Digital signal processing [M], Beijing: Beijing Institute of Technology Publishing house .1997; 3:50~52
[5] Chen Zhigao, the plum tree is broad. Based on TMS320F2812 active filter’s design. Micro computer information .2007; 21(2):158~159
