Abstract: This article has designed one kind based on the FPGA UART nucleus, this nucleus conforms to the serial communication agreement, has the modulation, the compatibility and configurable, suits applies in SoC. In the design uses Verilog the HDL hardware description language environment to carry on the design, the simulation in Xilinx under the ISE, finally inserted UART on FPGA the IP nucleus to realize electric circuit’s asynchronous serial communication function.
Key word: IP nucleus; UART; Verilog HDL; FPGA
Abstract:This article introduces the design of a UART core based on FPGA. According to the protocol of serial communication, this core has the characteristic of modularity and configurability, and is ideal for SoC (system on a chip). Verilog hardware description language (HDL) in the Xilinx ISE environment has been used for its design, compilation and simulation. The UART IP core has been implemented using FPGA technology.
Keywords:IP core; UART; Verilog HDL; FPGA
1 introduction
In the data acquisition system, often needs to carry on the asynchronous serial data transmission, at present widely uses RS232 asynchronous serial interface, like 8250, NS16450 and so on special-purpose integrated chip, although uses simply, actually has takes the electric circuit volume, the pin connection complex and so on shortcomings. SoC (System on Chip, on piece system) is in the ASIC design new technology, is take the embedded system as the core, take the IP multiplying technology as the foundation, the collection software and hardware in a body’s design method. Uses the IP multiplying technology, integrates on the FPGA chip UART, may increase system’s reliability, reduces the PCB board volume; Next as a result of the IP nucleus’s characteristic, uses the IP endorse to cause the overall system to be more nimble, but may also according to need to carry on the function the promotion, the expansion and the reduction.
This article uses Verilog the HDL language to compile the UART module, integrates on the FPGA chip it, constitutes on the SoC piece with the chip on other functional module the system.
2 The UART module design with realizes
UART serial data form as shown in Figure 1, serial data including 8 bit data (8 data bits), 1 outset position (start bit), 1 stop bit (stop bit), 1 bit check position (parity bit), altogether 11.
Figure 1. UART data format
UART modular structure as shown in Figure 2, left side transmits the latch, the transmission shift register and the logical control composition transmission module (txmit), right side receives the latch, the receive shift register and the logical control composition receive module (rxcver). The transmission module and the receive module besides use in common reset signal, clock signal and the parallel data line, has the respective input, output and the control logic unit separately.
Figure 2. UART modular structure
2.1 baudrate clock’s control
The UART nucleus contains a programmable baudrate generator, it gives the transmission module and the receive module provides the transmission data and the receive data datum clock, clock mclkx16 which the baudrate generator produces is serial data baudrate 16 times. It enters the n frequency division to the system clock, the formula is: mclkx16= system clock/baudrate *16, may obtain the expectation internal baudrate clock in view of the different baudrate hypothesis corresponding value.
2.2 transmission module design
The transmission module divides into three kind of patterns: The idle mode, writes down the data pattern, the shifting pattern. When the parallel 8 bit data read in the transmission module after the main line, the transmission module loads the parallel data in latch thr, then shifts in shift register tsr the data, produces the complete transmission sequence (including outset position, data position, parity check position and stop position), by corresponding baudrate from the tx transmission. Transmission module’s input clock mclkx16 is serial data baudrate 16 times, after the module interior its 16 frequency divisions, obtains baudrate clock txclk.
In transmits in the succession chart we to see the data-in is 8 ‘ b00001111, the verification position is the wonderful verification, has the verification position is ‘ 1 ‘. the tx end outputs the outset position in turn ‘ 0 ‘, 8 bit data ‘ 00001111 ‘, verification position ‘ 1 ‘. in the tsr shift register the data right lateral, the top digit makes up in turn in the first two right laterals ‘ 1 ‘, afterward in 8 shifting the top digit makes up ‘ 0 ‘.
Below transmits the module main segment, uses Verilog the HDL language to compile. Because initial and the shifting procedure is quite simple, here has not given.
always @ (posedge txclk or posedge reset)
if (reset)
idle_reset; // initial program
else
begin
if (txdone && txdatardy)
load_data; // loads the data tsr, and transmits the outset position
else
begin
shift_data; // tsr8 bit data shifting, and has the verification position
if (txdone)
tx <= 1 ‘ b1; // outputs the stop position
else if (paritycycle)
tx <= txparity; // outputs the verification position
else
tx <= tsr[0]; // output data position
end
end
Figure 3. Transmission succession
2.3 Receive module design
The receive module also divides into three kind of patterns: Idle mode, examination outset position pattern, shifting pattern. First catches the outset position,
Examines unceasingly under the mclkx16 clock from the rx end data-in outset position, when after examining the outset position, the receive module transforms by the idle mode into the shifting pattern, and 16 frequency division mclkx16 produces the rxclk baudrate clock. This time the rxclk clock’s rise along is located at serial data each, the such following data in each center point sampling, can filter the noise effect effectively. Then along reads in by the rxclk control in the rise the data position shift register rsr the rsr[7] position, and rsr right lateral 1, according to the process 8 bit data read in rsr completely, and stops producing the rxclk baudrate clock. After the judgment parity check, the frame structure and overflow the sign correctly, in the rsr register’s data reads in the rhr data lock to save in the register, finally data which completes by 8 bit data bus out transformation.
rxclk clock’s production dependence judgment outset position, in outset position ‘ 0 ‘ center point production, and after examining the stop bit stops, as shown in Figure 4.
Figure 4. The receive module baudrate clock has the succession
The receive shifting segment is as follows:
task shift_data;
begin
rsr <= rsr >> 1; // register right lateral
rsr[7] <= rxparity; // data loads rsr[7]
rxparity <= rxstop;
rxstop <= rx;
paritygen <= paritygen ^ rxstop; // produces the odd and even quite to symbolize
end
endtask
By the succession chart may see that to a complete data frame’s receiving process, after hunt and the idle symbol catches the outset position, produces the rxclk baudrate clock, the serial data shifts in rsr, in rsr the data right lateral top digit makes up zero. When the outset position ‘ 0 ‘ shift after rsr[0], receive module in the next clk rise along returns idling condition, after returns idling condition, has data shifting to complete interrupts rxrdy, the data may from 8 bit data main line read-out.
Figure 5. Receive succession
3 UART syntheses
Procedure after simulation confirmation, must synthesize produces the IP nucleus and inserts in FPGA. Uses Xilinx Corporation’s Xilinx the ISE tool to synthesize the UART module, FPGA selects Xilinx Corporation’s Spartan-IIE xc2s50E, system clock 40Mhz. After Xilinx ISE synthesis, the resources use result as follows shows, indicated that use few FPGA Slice and the LUT unit may produce the UART nucleus.
Table 1. Resources service condition
|
Number of Slices |
108 out of 768 |
14% |
|
Number of Slice Flip Flops |
90 out of 1536 |
5% |
|
Number of 4 input LUTs |
195 out of 1536 |
12% |
|
Number of bonded IOBs |
25 out of 102 |
24% |
|
Number of GCLKs |
1 out of 4 |
25% |
The UART endorse divides into nimbly receives and transmits two parts, may according to need to choose the use, saves the system resources; Some control mark character may also according to need to delete voluntarily and to expand. Finally will integrate has UART the nucleus FPGA data acquisition system and the test panel carries on the asynchronous serial communication experiment, corresponds the data after the examination to indicate that uses the UART nucleus to transmit the data stabilization to be reliable.
4 concluding remark
Uses the UART asynchronous serial communication connection in the data acquisition system to take data acquisition system’s short distance serial communication frequently. Was opposite in the traditional UART chip, integrated has UART in FPGA the function IP nucleus to be more advantageous in enhances data acquisition system’s reliability and the stability, reduced the electric circuit volume. This article designs UART the IP nucleus through the simulation confirmation, after the synthesis, the translation, inserts FPGA, the success applies in data acquisition system’s port correspondence.
Reference
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