Abstract: Introduced one kind based on EZ_USB the FX2 monolithic integrated circuit’s conventional data transmission module, discussed USB the controller EZ-USB FX2(CY7C68013) performance and the transmission mode and gives this system’s hardware to realize the plan. Through uses GPIF which Cypress Corporation provides the Designer tool to develop GPIF (general programmable connection), defines the good profile descrptor in advance, through stimulates the GPIF function to realize the data transmission.
Key word: EZ_USB FX2 monolithic integrated circuit, general programmable connection, profile descrptor, data transmission
1 introduction
Today which weeds through the old to bring forth the new unceasingly in each kind of computer periphery connection, the USB connection has become nowadays on gradually the personal computer one of most important connections, and is quick by its transmission speed, characteristics and so on easy to operate and low in price become nowadays the common consumption electronic products and on the industrial control equipment the essential connection. The USB connection the transmission speed may achieve 12Mb/s under the full speed pattern, the high speed pattern achieves 480Mb/s. In FX2 inlays the enlargement mode 8051 micro control essences, and uses 8051 standard sets of instructions, but the instruction carries out the speed compared to standard 8051 quick 5~10 times. Because in this essence’s bus cycle is composed of 4 clock cycles, but standard 8051 bus cycles are composed of 12 clock cycles, moreover, its clock rate is 24M or 48M, but the standard 8051 clock rate is 6M or 12M. USB has the hot drawing to insert the function hotly, may connect many USB auxiliary equipment. This article is precisely based on this new bussing technique, selects USB2.0 chip CY7C68013, Xilinx Corporation’s FPGA XC2S50E and pair of mouth RAM CY7C026 composes an general data transmission module, in any kind of data acquisition system, may deposit after the gathering system processing data in pair of mouth RAM or other memories, connected may realize again with this USB transmission module with the PC main engine’s correspondence. Here introduces CY7C68013 emphatically the hardware interface design and the GPIF function.
2 hardware designs
2.1 system diagrams
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Figure 1 |
System hardware diagram as shown in Figure 1. Mainly by data-carrier storage pair of mouth RAM, FPGA, the built-in MCU USB connection chip and the main engine four parts is composed.
2.2 hardware work process
Regarding data transmission module’s core of component USB2.0 controller CY7C68013, it already is responsible for the USB business process also has both processor’s control function, realizes protocol conversion between the main engine and the USB equipment’s. After the system adds the electricity replacement, according to the USB standard reply, carries on the equipment recognition and the main line enumeration, namely the computer examines has the equipment insertion, sends out the inquiry to request automatically, the USB equipment responds this request, sends out equipment’s Vendor ID and Product ID, the computer acts according to these two ID to load the corresponding driver, and gives the domination 8051,8051 carries on through the main line to system chip each parameter the initialization establishment. CY7C68013 including 1 8051 processors, 1 serial interface engine (SIE), on 1 USB transceiver, 8.5KB piece RAM, 4KB FIFO memory as well as 1 general programmable connection (GPIF). The data-carrier storage high speed pair of mouth static state RAM CY7C026 specification for 16K×16, the access speed is smaller than 25ns, has the true twin port, may simultaneously carry on the data access, two ports have the independent control holding wire, the address wire and the data line, moreover through main/may expand the storage capacity and the data width conveniently from the choice. Through the chip signal quantity marker, the left and right two ports may realize chip resources sharing, the CY7C026 data transmission mainly pass “the mailbox” to realize. So-called “the mailbox” points to the chip to take memory’s high address 3FFF the left port “the mailbox”, 3FFE takes the right port “the mailbox”. When the left port reads in the data the right port “the mailbox”, the right port’s INTR base pin will produce the signal of stop, namely the INTR base pin will set lowly. After the right port reads this data, signal of stop automatic reset. In this design may select 0×1024~0×5119 in pair of mouth RAM and 0×5120~0×9215liang a buffer, the address space is 4KB willfully. After double mouth RAM by write data, produces the signal of stop in the right port to receive by FPGA. After FPGA receives the signal of stop, produces an interrupt request signal immediately to CY7C68013, “inquired that” USB whether to prepare to receive the data. What if CY7C68013 returns is “prepares” the signal, then FPGA reads the left port “the mailbox” the data. When the definition reads when the data is “00″, FPGA is the 0×1024 buffer starts the reading from the address; When reads when the data is “ff”, is the 0×5120 buffer starts the reading from the address, has realized to the data double cushion read-write. Because the pair of mouth RAM address wire is 14 [13:0], GPIF only then 9 address wire [8:0], therefore carries on the expansion through FPGA to the USB address, after USB produces the handshake signal for FPGA, in GPIFADR[8] drops along triggering, high address A[13:9] automatic Canada 1, thus combines address bus AB[13:0].
3 software designs
3.1 GPIF connection pattern
CY7C68013 has three kind of available connection patterns: Port, GPIF master control and from FIFO. In “the port” under the pattern, all I/O pin may take 8051 general I/O mouths. In “from FIFO” under the pattern, the exterior logical or exterior processor is direct and FX2 vertex FIFO is connected. Under this kind of pattern, GPIF is not activated, because the external logic may positive governing FIFO. Under this kind of pattern, the outside master control end already may be the asynchronous system, may also be the synchronous mode, and may be the FX2 connection provides own independent clock. “GPIF master control” the connection pattern uses PORTB and PORTD constitute to four FX2 vertex FIFO (EP2, EP4, EP6 and EP8) 16 bit data connections. GPIF takes the internal master-control unit and FIFO direct connected, has 6 programmable control output signal (CTR0-5) and 6 general ready input signal (RDY0-5), the user may through the programming decide that the control signal the output state, i.e. the chip after what ready signal receiving carries out the corresponding operation. The user program deposits in is in chip interior RAM in profile description [1]. Because the GPIF running rate is much quicker than FIFO, therefore its succession signal has the very high programming resolution. Moreover, GPIF already may use the chip internal clock (48MHz), may also provide [2] by the exterior oscillating circuit. Therefore, this system uses the GPIF pattern the data transmission plan, so long as the output signal and the ready signal make the corresponding combination, may realize many kinds of complex control succession [5].
3.2 GPIF profile code
To the GPIF programming, may use Cypress Corporation to provide based on Windows contact surface development kit GPIF Designer. It has provided a very friendly visualization window, makes the simple revision on the graphical interface, may produce named *.c about the profile descrptor source document. This source document mainly by two parts of constitutions, namely initial variable (WaveData, FlowStates and InitData) definition and GPIFInit () realization. In the initialization function is mainly the disposition and GPIF related register [3]. In the GPIF procedure memory block ordinary circumstances saves 4 groups of profiles, respectively is Single Read, Single Write, Fifo Read, Fifo Write. Embarks from this system requirements, presently supposes CY7C68013 is Fifo the Read pattern, lets in GPIF Slave FIFO and in the USB correspondence the vertex cushion direct establishment connection, the data transmission no longer needs CPU participation [4]. Double mouth RAM reads operation succession as shown in Figure 2, after the address produces at least 25ns, in the data line data is effective. This design uses the 48MHz crystal oscillator, each clock cycle is 21ns, therefore establishes the data working life in the GPIF Designer profile is 4 CLK, can definitely satisfy the address working life the request.
Figure 3 is USB in batch read pair of mouth RAM the data profile description. When system initialization, under the FPGA control, double mouth RAM selects patches or strips of land as worth saving for seed signal CE, the output to enable OE as well as read-write gating signal RW is supposed for the effective condition. When S0, address automatic Canada 1, the data is then effective, after holding renews a contract 84ns, the start next transformation. May see between the address and the data corresponding relationships clearly from the chart.
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Figure 3 |
3.3 firmware program design
The firmware program code development is mainly (as shown in Figure 4) according to the system requirements design corresponding procedure frame chart, then the transfer firmware function storehouse (Ezusb.lib) provides the function carries on the programming. Because used GPIF, must carry on the initialization to the vertex and enumerate, then established the duty in the duty processor. Firmware program’s compilation selects Keil Corporation’s KeilC5l compiler (V6.10). It was the 805l micro controller’s software development has provided the C language environment, simultaneously retained the assembly code highly effective, the fast characteristic, was opposite is more nimble in the traditional assembly development environment, highly effective and easy to use. Carries on the translation the code in the KeilC51 environment. Translation, downloads the firmware code to the USB monolithic integrated circuit, may realize GPIF to carry on many bytes to read and so on operations. When the procedure starts, the firmware construction will carry out the following step:
(1) establishment all internal behavior variable, namely establishment outset starting value.
(2) transfer user’s initial establishment function TD_ Init (). After treating the returns, the firmware construction will establish the USB connection not to become the disposition condition, and will enable the interrupt.
(3) in the 1s time-gap, starts the equipment to enumerate (ReNumerate) again, until establishes the (SETUP) wrapped gift to receive the vertex 0.
(4) when after the SETUP wrapped gift is examined, the firmware construction will start and its cooperation work divider. But this work divider repeatedly will carry out the following work according to the order:
①Transfer user function TD_ Poll().
②Whether to decide the standard equipment request is undecided (or waiting decision). If had decided that it will analyze the order which will receive to request, and will perform to respond [6]. Namely examines whether to have the standard equipment to request, if has, then the executive order and makes the corresponding operation.
③Whether to decide the USB core already reported USB stops the (Suspend) event. If had decided that it will transfer user function TD_Suspend(). If obtains the success the returns, then tests replies the (Resume) event. Otherwise, if has not examined, it will put in the microprocessor stops in the pattern. When the reply event is examined at the appointed time, will transfer user function TD_Resume(), and continuously rebound to step③. If from the TD_Suspend() function has not received the successful returns, jumps continuously again to the step③[6].
Figure 4
The firmware program writes down has two ways. Way one: Through chip I2C bus interfacing exterior EEPROM, the firmware code passes the overroasting to write beforehand reads in EEPROM, when on USB equipment electricity movement, the firmware code writes down through the I2C main line EEPROM. EZ-USB supports exterior EEPROM to download the firmware through the main line, this way enables the exploiter to be possible to download 8051 procedure codes from the periphery hardware, but does not favor in the equipment phase of exploitation use. Way two: Uses this chip unique soft disposition function, saves the firmware program in the computer, when this equipment turns on the USB electric cable, because EZ-USB has ability which enumerates, therefore after initialization enumeration, the user only needs in development software UsbControlPanel which provides through Cypress Corporation the Download item, may write down the firmware in the control chip. This method is the soft operation completely, does not need the extra hardware equipment, convenient procedure revision debugging.
4 concluding remark
Using Cypress Corporation’s USB main line specific interface chip CY7C68013, has completed based on the GPIF conventional data transmission module hardware and the software design. The chip programmable characteristic will enhance the system work reliability, the data will not lose, antijamming ability, was advantageous for the data the transmission and processing. Moreover, the USB equipment has the characteristic which “inserts hotly pulls out” and namely inserts namely uses, the easy to operate, does not need to close down restarts or turns on the engine case to carry on loading and unloading, has the good application prospect and the very high use value.
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