1 introduction
The majority receivers must process the dynamirange very big signal, this need makes the gain control, produces by the overload protection or some level intermodulations, adjusts demodulator’s work to optimize the work. In modern radio reception installment. The variable gain amplifier is electrically controlled, when and in the receiver uses the attentuator, they usually are the continual attentuators which controls by the variable voltage. The control should be smooth, and input signal energy usual doubling number relations (linear decibel). In majority situations, because declines, AGC usually uses for to survey inputs demodulator’s signal level, and through reaction control electric circuit signal level control in request Fan Tongnei.
2 system system design
In this design, after front end TD_SCDMA radio-frequency signal RF input, after passing through MAX2392LING under the intermediate frequency the frequency conversion demodulation, carries on gain processing. VGA output signal after the ADC transformation becomes the digital intermediate frequency signal, (received signal processor) processes the output after RSP is the IF digital signal. After the IF signal may undergo AGC control algorithm processing, controls VGA the gain. The AGC gain control algorithm realizes in the numerical part, in this design, the AGC electric circuit may enhance the link effectively the dynamirange ( 25~-105 dBm), enhances ADC output SNR, enables DSP to realize the Dw-PTS synchronization easily. AGC the dashed line frame shows in system’s position like chart 1:
3 AGC system’s FPGA realizes
According to AG
C realizes the function, divides into FPGA the AGC module the following several parts to realize:
3.1 data main route module
Comes 10 two’s complement data I1 and Q1 from the RSP connection, after striving for the data which the index module transmitted the pre-enlargement which to increase GAIN2 multiplication obtains (still to take 10 two’s complement data) to be going to transmit to the CIC average module, simultaneously must with strive for the enlargement which the index module transmitted to increase the GAIN3 multiplication separately, then adopted detruncation processing, took 8 two’s complement data, I1 ‘, Q1 ‘, output in DSP.
3.2 computation downward synchronous code power (SYNC_DL) module
Calculates the downward synchronous code power (SYNC_DL) module to correspond to Figure 2 the judgment part, is in AGC the most important algorithm computation. TD_SCD-MA each frame has 6 400 code pieces, in its 5 ms time not continuously, therefore can only extract downward synchronous code (SYNC_DL) the performance number, controls VGA take this as the basis the voltage value.
TD_SCDMA frame structure knew by Figure 3 that downward synchronous code (SYNC_DL) in the downward pilot frequency time slot (DwPTS) launch, the SYNC_DL length is 64 code pieces, in its left side and right side has 32 and 96 code piece protection time slot (GP) respectively. Therefore, used 3 different methods in the FPGA Chinese Communist Party to calculate its performance number.
The method one acts according to the linear rectification in FPGA the principle computation downward synchronous code 64 code piece power (AGC module chart 2 the dcmt part). Considered that TD the frame structure, protects time slot GP the power to be very small, therefore looked from receiving power’s time distribution, compares the SYNC_DL section with GP the power to be big. When divides around SYNC_DL with the SYNC_DL section’s sums of 64 yard piece sum of the 32 code piece adding together, when finally is bigger than 3, may judge SYNC_DL the approximate position. Therefore, based on this method, FPGA takes 6 400 code pieces in 5 ms cycles, every 64 code piece makes the integral, rolls forward in turn the computation, simultaneously makes the division operation, finally then calculates SYNC_DL in a 6 400 code piece position and the energy, controls VGA by the voltage and the following computation. However this method is very good in the signal quality, signal strength quite great time only then calculates accurately.
The method two data which passes on by the DSP side basis, examines SYNC_DL through the coherent detection law the exact location, and transmits this location parameter for FPGA. After FPGA receives this point the position, stands already stops the performance number which uses its own linear rectification to extract, passes on the SYNC_DL position according to DSP, after calculating this point 64 code piece integral valve, takes SYNC_DL the total output, and controls VGA by the voltage (AGC module chart 2 the dwpts part). By now strove for the total energy is quite precise (position which DSP provides compared to FPGA own linear rectification to strive for precisely), but the speed is quite slow.
Method three, when the signal intensity becomes very weak, the signal possibly submerged in the middle of the noise. Regardless of by now could not calculate the SYNC_DL position and the energy by the FPGA linear rectification or the DSP coherence technique. In this case, thought that the signal is continual in 5 ms time domains, the energy is balanced, FPGA asks the 5ms frame the mean value, takes SYNC_DL by the power, and controls VGA (AGC module chart 2 the CIC part).
3.3 ask the logarithm operation module
In this module, the performance number which obtains above carries on asks the logarithm operation, reduces the data the operand. Realizes with FPGA when strives for the logarithm operation, may the first data normalization between 1~2, then through the data square boost derives the highest order the method by the position to extract asks the data the binary value. Supposes the independent variable X normalization in sector [1,2], may express with the binary data is 1.X1X2…Xn, then asks to the value in sector [0,1], may express with the binary data is 0.Y1Y2…Ym, thus the available mathematical method expression is 20.Y1Y2…Ym=1.X1X2…Xn, the question sums up to ask Y1Y2…Ym. The above equation about nearby two simultaneously the square, may obtain 2Y1Y2…Ym= (1.X11X21…Xn1) 2, may overthrow Y1 from this. (X for known, if right side the equality the data is smaller than 2, then Y1=0; Otherwise, if is bigger than or is equal to 2, then after Y1=1) extracts Y1, may derive 20.Y2Y3…Ym=1.X11X21…Xn1, likewise may overthrow Y2. Ex analogia, may extract to value everybody.
When carries on the FPGA design, may design a square comparison unit to extract in turn to the value, simultaneously must pay attention to the system resources which needs to consume.
3.4 ask the index operation module
After asking the logarithm module, a group data transfer to IIR, another group data must transmit to DSP in carries on the algorithm operation, therefore, needs to increase one to ask the index module, delivers in DSP after the logarithm module operation’s result reduction original data. The index trades the bottom formula to be possible to know: 2x=ex1n2, may know by the hyperbolic function definition and the characteristic: ex=sinh(x) cosh(x), but works as independent variable x when [- π/4,7c/4] scope, may use FPGA IP CORE (the CORDIC algorithm) to realize the hyperbolic sine and the hyperbolic cosine, therefore when the FPGA interior asks take 2 as the bottom exponential function, may the first independent variable normalization in [0,1], then the independent variable be multiplied by often coefficient 1n 2, as a result of ln 2< π/4, therefore may ride newly the data takes the new independent variable, extracts its hyperbolic sine and the hyperbolic cosine after IPCORE its adding together, then obtains the index function value which needs.
3.5 IIR feedback module
IIR feedback module including 3 parts: IIR filter unit, saturated instead
Feeding unit and VGA control unit, after the IIR filter unit will be responsible to ask the value which and the reference value comparison, the logarithm module will obtain will obtain error information Uerr will make the IIR filter computation to obtain Ufilter, then the basis related algorithm will calculate Urssi. After the saturated feedback unit is responsible Urssi and the saturation limiting data comparison, obtains error voltage Uerr2, then extracts U2 according to the related algorithm to deliver asks the index module, can thus ning error feedback gain Gain2. After the VGA control unit is responsible to carry on Urssi saturation limiting, obtains output control voltage Uda, after the quantification, after the digital-analog transformation, thus controls VGA.
3.6 CIC average modules
When AGC uses in the WCDMA system, may the judgment part remove completely Figure 2, joins this CIC average module. The CIC average module is responsible for I1 which and Q1 extracts the pre-enlargement module takes the independent variable, ‘ =I1*I1 Q1*Q1 extracts P1 ‘ through power algorithm P1, then 6 400 operating frequencies is 1.28 MHz P1 ‘ the average, obtains the operating frequency is 1.28 MHz P1. After similarly obtains P2, extracts P1 P2 again.
In FPGA regarding the additive operation, realizes the part pure integer adding together algorithm and other part of decimal adding together algorithm including CIC. And the CIC arithmetic portion’s operational data is binary 10 has the sign digit; Regarding the multiplication operation, realizes a part pure integer square algorithm, CIC including CIC to realize the part often coefficient decimal multiplication algorithm.
4 conclusions
The above introduction realizes the AGC algorithm in FPGA, passes through the project the verification test, the effect is quite good, DA selects ADS the 5621, VGA voltage regulation scope between 0.3~1.8 V, altogether 45 dB regulation bands, therefore AGC in 10~-35 between the control action, the signal is lower than time - 45 dBm, the VGA voltage maintains 1.8 V maximum values; When is higher than 10 dBm, the VGA voltage maintains at smallest 0.3 V. After the test, FPGA may search SYNC_DL in 25~-105 dBm scopes the position.
This kind of AGC algorithm, the computation is relatively simple, the operating speed is quick, not only may use in the TD_SCDMA signal, when computation downward synchronous code energy modifies slightly, only makes the CIC average calculating operation, then applies in the WCDMA signal.
