Virtex-5 FXT FPGA - ultimate system integration platform
Because numerous increases the cost which and the time budget unceasingly with the evolved standard, the harsh processing request as well as reduces unceasingly, the digital convergence time has accelerated to the FPGA core value position dependence. These core value position is: The flexibility, the scene may promote ability, outstanding signal processing ability, the quicker product going on the market time, to lower the standard which the risk, the adaptation evolve unceasingly as well as to reduce the system cost. Virtex®-5 platform establishment in these rich value foundation, in addition high speed serial connection function and embedded handling ability, thus constituted the ultimate system integration platform.
Virtex-5 the FXT platform was unified the field standard 550MHz PowerPC® 440 embedded processor essence, DSP and high speed serial I/O function FPGA only, its unequalled system integration rate might support the correspondence, in the audio frequency video frequency broadcast, the military and the aviation, the industry, the science as well as the medical market high performance application well. Using Virtex-5 the FXT platform, this kind of application’s designers may enhance the integrated system performance, the minimum circuit wafer order of complexity and reduce the system cost.
Virtex-5 series
Regardless of provides in the product usability for the customer the multiple options aspects, Virtex-5 the series FPGA platform is field leading high density 65nm the FPGA product. The Virtex-5 series is Virtex the series FPGA 5th generation of product. Based on its unique ASMBL construction, the Virtex-5 series provided the platform altogether 24 model of components which four domains optimized to supply the customer choice:
· LX - optimizes in view of the logical application domain
· LXT - in view of supports the low power loss serial connection logic application domain to optimize
· SXT - optimizes in view of the support serial connection’s DSP application domain
· FXT - optimizes in view of the support high speed serial connection’s embedded processing application domain
This series component has provided a series of innovation characteristic, including:
· New CLB and enhancement wiring technical support ultra-fast ExpressFabric™ technology
· LXT, SXT and the FXT platform provides the PCI Express® vertex module which integrates completely
· LXT, SXT, the FXT platform provides three patterns which integrates completely (0/100/1000 Mbps) the ethernet MAC module
· Provides ECC choice 36Kbit the twin port BRAM/FIFO module
· Brings PLL 550Mhz clock management pipeline (CMT)
· Supports ChipSync technology SelectIO
· The second generation of sparse zigzag (Sparse Chevron) seals the technical support enhancement pin output function
· The multi-potential flow management and many kinds of fine grain frame size convenience carries on the partial reshuffles
Virtex-5 the FXT platform increases the system integration principal characteristic includes:
· Complete integrated PowerPC 440 processor module and 128 interconnections
· High performance GTX 6.5 Gbps serial I/O
· XtremeDSP™ logical piece (DSP48E logic piece) optimum composition
As soon as table 1:Virtex-5 the FXT product looks at
PowerPC 440 processor modules
The PowerPC 440 processors already widely applied in the match spirit think in the segmentation market numerous system application which company high density FPGA faces, and has undergone the test and the confirmation. Virtex-5 FXT FPGA took the lead to provide has simultaneously conformed to two field standard PowerPC 440 processors, its enhancement’s system performance might support the designers to realize advanced easily fast may promote the embedded processing application. Each processor integrates the 32KB instruction and the 32KB data buffer, may provide reaches as high as 1,100 DMIPS under the 550MHz clock the performance.
Enhances the system processing performance the key is largely through the multichannel, highly effective, the concurrent high speed data visit sharpens the conceptual data handling capacity. In order to serve this purpose, the new integration’s 5×2 crossbar switching type processor interconnection construction and the PowerPC 440 processor tight bonds, provide concurrent I/O and the memory visit ability (Figure 1). This integrates highly the construction supports 5 to advocate PLB (processor local bus) the connection and two from the connection, four independences receives and dispatches the full-duplex channel DMA port and a private memory bus interface, therefore the memory band width is highest may reach before this solution 5 times. Under the new hard coring crossbar switching type construction management, the system support visits many 128 main lines (are originally 64) the data concurrently, thus further expands the system handling capacity. The advanced PLB construction supports the high volume of goods handled 128 connections, may reduce the system bottleneck, thus maximized processor, between crossbar switch type exchange structure as well as soft IP logic data transmission ability. 
Chart 1.PowerPC 440 modules including the PowerPC 440 essences and new interconnection construction
Forms what with this new construction supplementary is, this platform integration’s enhancement high performance auxiliary processor control unit (APU) the connection permission user may construct the auxiliary processor to carry out the non-PowerPC 440 set of instructions instructions. This for application and so on in video processing, 3D data processing and floating point arithmetic special-purpose associations processed the engine or the user special-purpose has custom-made the guide to provide the support.
High speed serial connection ability
Virtex-5 the FXT platform supports most popular digital I/O and several thousand megabits (multi-gigabit) the serial I/O technology, provides reaches 24 entire function RocketIO™ milliardfold level transceiver (GTX). These enhancement’s transceiver may support now from 500Mbps to the 6.5Gbps data rate. Virtex-5 FXT the GTX transceiver is in the present Virtex-5 series the speed is quickest, not only expanded Virtex-5 LXT and in SXT FPGA obtains the confirmation transceiver construction, simultaneously has also facilitated in Virtex-5 LXT, SXT & design transplant between the FXT platform.
The typical power loss which when attaches raises data rate performance 6.5Gbps speed each channel consumes only then 200mW. When moves when the low 3.75 Gbps speed, each channel power loss only 100mW.
Besides the higher serial I/O performance, but also strengthened some other essential characteristics. In order to enhance these high speed signals the signal integrity, integrated 4 tap decision-making feedback equalizer (DFE), the linear balancer and the transmission pre-emphasis compensation. The decision-making feedback equalizer (DFE) is one kind of misalignment balancer, before the use, examines the decision-making to eliminate the current demodulation pulse between the mark to disturb (ISI). The DFE merit is its work in the non-noise quantization level, therefore its output has nothing to do with the channel noise.
The GTX transceiver has provided one new nimble speed converter, or the gear box, supports the main leading agreement 8B/10B, 64B/66B and the 64B/67B code and the synchronization. The independent transmission and the receive data stream support the full-duplex to operate.
Used in PCI Express®, Gigabit Ethernet and XAUI complete agreement Bao Wei designs has provided a low risk way successfully. This agreement package may also be SONET OC-48/SDH STM-16 and CPRI (Common Public Radio Interface) provides the special-purpose agreement parameter to report, can thus when uses the new serial agreement has the confidence. Each standard agreement package includes in view of the specific agreement physics level characteristic description report, the interoperability and the compatible report, the intellectual property rights (IP) the essence as well as the technical documents, supports the user highly effective and the low risk realizes the standard high speed serial agreement in Virtex™-5 FPGA.
System-level digital signal processing
Virtex-5 FXT the platform DSP performance has made the significant contributions regarding its achievement ultimate system integration platform’s value. Basically, compares with the traditional DSP processor’s fixed construction, FPGA provides the DSP performance is higher than several magnitudes. At present more and more correspondences and the multimedia systems need to be higher than 4MSPS the DSP performance, therefore had already far exceeded the majority independent DSP processor’s limit.
May construct the highly parallel processing construction conveniently using FPGA, can complete the complex algorithm in the single clock cycle, thus the monolithic component may provide the hundreds of MSPS performance. In the so high DSP performance capability, the designers may choose reduce FPGA the clock rate to save the power loss, may also choose realizes the multichannel to reduce the system cost and to reduce the bill of materials cost (BOM).
Virtex-5 FPGA the series high performance DSP function’s key is its DSP48E logic piece. These logical piece can carry out the majority digital filter first floor operation multiplication accumulation operation highly effective. Constructs the multiplier module including in the FPGA support to realize the wider input filter by the special hardware, thus enables the DSP designers to be possible to obtain a higher performance. Virtex-5 FXT FPGA provides the high ration the DSP logic piece (including to reach as high as in 384 to construct 18×25 DSP logic piece), may provide under the 500MHz clock rate reaches as high as 192 GMACs/second performance. Compare with the Virtex-4 in 18 x 18 multipliers, Virtex-5 in the DSP48E logic piece’s multiplier achieves 25 x 18. Gathers with the wider data way and 96 accumulation output appropriate match may support the high accuracy single precision floating point calculation. At the same time, DSP48E logic piece when the high accuracy filter work expends the resources are also less.
Carries out the speed besides the fast logic, the high performance system also needs the processing unit to have the fast turnover mass data ability. Virtex FPGA provided two supplementary methods to construct the highly effective memory structure:
· The search table (LUT) in logical organization’s storage location constitution’s distributional RAM may support realizes 64 shift registers.
· 36Kb the module embedded BlockRAM structure may provide reaches 16.5 Mb much the memories.
Because the embedded BlockRAM structure on the chip is with the DSP48E logic piece neighbor, therefore they to have provided the superelevation band width method to the filter construction supply data. The FXT platform may provide reaches as high as 16.5Mb the internal memory and 163 GBytes/s gathers IO the performance the total IO band width, may satisfy the system-level request.
The high system integration rate further enhances the performance
Virtex-5 FXT the FPGA system integration rate’s enhancement further enhanced the performance, this is mainly because the entire platform processing subsystem improves composition effect. Uses the crossbar switching type interconnection construction to replace the list sharing main line interconnection way, uses the network which many independent main lines compose to come parallel to complete the data transmission, thus improved the overall system performance. Many operation operations might also carry on, reduced the jamming and the standby period. Further sharpened the system data handling capacity using 128 data transmissions.
Figure 2. in Virtex-5 in the FXT platform, the new PowerPC 440 processor module connection passes the perfect exchange type interconnection structure and the hard core three mold ethernet MAC connection. 
For example, in Figure 2 shows the milliardfold ethernet design demonstrated in the crossbar switching type structure the memory controller (in structure produces soft controller) and memory controller connection (MCI) model connection. Because this is an independence in other accessing operation (for example peripheral device processing) private port, therefore always retards and the band width also obtains the improvement. The peripheral device (soft) attaches to the PLB46 main line, and connects in the crossbar switching structure independent host PLB (MPLB) the port.
A milliardfold ethernet connects the system one of through new integration’s hardware DMA controllers. DMA engine also connection to crossbar switching structure. When need, this exchange constructs into the DMA engine and main storage’s connection way. The milliardfold ethernet design has also used Virtex-5 FXT in platform hard core milliardfold ethernet MAC, therefore may use less resources and reduce the power loss.
Above platform’s kilomegabit ethernet system with platform’s same system compares based on Virtex-5 the FXT based on Virtex-4 the FX, the performance enhanced 2.7 times. This performance promotion is refers to the overall system handling capacity the promotion, but must merely is the processor, the peripheral device or I/O.
Using
The numerous complex applications like wired and the wireless communication, the audio frequency/video frequency broadcast, the aviation and the national defense as well as the industrial science and the medical service and so on four big essential professions proposed the high multiplication’s harsh request, causes Virtex-5 the FXT platform multiplexed system integration to arise at the historic moment. In these market’s customer thought of the FXT product line regarding the match spirit the development to make the significant contributions, their common impetus, enabled the component disposition to be able to satisfy the FPGA logic, embedded processing, DSP, the memory and serial IO and so on all aspect request.
Correspondence
The wireless communication market is a change is fast, and has the challenging environment. The system design personnel always face provide the new solution the challenge, either is to reduce the existing product cost, either provides the non-risk the infrastructure migration method, (for example 3GPP-LTE and WiMAX) provides the highly effective support for existing as well as the next generation technology.
Figure 4. uses Virtex-5 the FX100T component’s next generation wireless base depot (LTE). 
Uses the match spirit in this application to think of Virtex-5 FXT FPGA may guarantee the processor subsystem, the DSP tax to be able between the FPGA structure as well as the high-speed service tight bond and the integration. This LTE baseband reference system’s hardware and the software unit’s integration uses the standard hardware circuit wafer component to realize in monolithic Virtex-5 on the FX100T.
Audio frequency/video frequency broadcast
The IP video frequency (Video-Over-IP) the system using compression standards and so on MPEG-2 carries on the code to the video frequency class. Then, this system (IP) realizes in the network using Internet agreement between the diversity to code the potential flow the transmission. The non-time key’s other traffic flow is different with the network, the video data must observe the strict grade of service (QoS) to want the vacant position to be able to satisfy the video frequency request.
At present using the video frequency processor, uses in accelerating or completing the real-time algorithm programmable logic, as well as uses in the network service the ethernet solution constitution piecemeal type solution also being possible to satisfy these requests. But Virtex-5 FXT FPGA was industry jieshou has realized all these functions on the single programmable SOC chip.
Chart 4.IP video frequency (Video-Over-IP) system integration chart demonstration high-level request
Ultimate design solution
Very obviously, this ultimate system integration platform needs a unified design environment. This design environment may display the match spirit to think of the system-level platform unit which and the rich function fully in the FPGA component integrates, guarantees the best design productive forces and the system performance.
Therefore, the match spirit thought of the company to promote ISE™ Design the Suite 10.1 edition of software suites. This suite has provided on the foundation collection nimble FPGA logic, embedded processing, high speed serial IO, DSP, the board for the system design group the memory design and the connection as well as may have custom-made the IP module all developments which and the debugging aids high-level the solution needs finally in a body. The ISE design suite integrated many kinds of has won the great honor repeatedly the design tool and the technology, might facilitate and speed up the system development. This suite including the following tool:
FPGA design environment
- ISE Foundation™ software and ISE WebPACK™ software (free download)
- PlanAhead™ design and analysis tool as well as PlanAhead Lite
- SmartXplorer™
Embedded processing design environment
- Xilinx Platform Studio and embedded development suite (Embedded Development Kit (EDK))
DSP design environment
- System Generator for DSP
- AccelDSP™ Synthesis Tool
Platform debugging support
- ChipScope™ Pro tool
- ChipScope Pro serial I/O tool collection
As a ISE Design Suite part, ISE the Foundation software is the FPGA logical design tool collection which the field is second to none. Provides together with ISE Foundation also has the match spirit to think of the company PlanAhead project analysis tool, for as adaptive thought of the FPGA component’s design as the match spirit to provide the formidable analysis and the layout function. In addition, the SmartXplorer technology enables the designers to complete a more multiple physics to realize every day, simultaneously the performance may also further enhance reaches 38% much.
To the embedded system design, Xilinx Platform Studio and embedded development suite (EDK) has provided a comprehensive hardware and the software design environment, may accelerate embedded system’s design speed.
The XtremeDSP development tool bag has included System Generator for DSP and the AccelDSP comprehensive tool. Using these tools, may welcome conveniently using The MathWorks™ company Guang Shou MATLAB® and Simulink® DSP the modelling environment development DSP algorithm realizes in the FPGA hardware.
ChipScope Pro may through aim at “the platform” component’s debugging, can discover deep Tibet in the hardware and software’s embedded flaw. ChipScope Pro Serial the I/O tool collection support user appraises and the survey high speed serial I/O channel’s dislocation rate fast (BER).
Summary
The system integration regarding the electronic profession is throughout an item the essential method which has the strategic sense value to be unable to weigh. May reduce the cost through the system integration, enhance the performance and to cause the system-level technology to move toward the next milestone, can complete the work the original need entire engine case to reduce to the circuit wafer size, realizes the function the circuit wafer to integrate IC (ASIC and ASSP).
Unifies FPGA the flexibility and programmable ability these basic superiority, embedded processing, the DSP performance and the high speed serial connection ability’s formidable fusion causes the match spirit to think of company’s newest product Virtex-5 FXT FPGA to become the ultimate system integration platform.
