Abstract: Introduced the digital audio frequency broadcast (DAB) channel coding’s principle and the key technologies, and realize the DAB channel encoder using monolithic FLEX10K100 series FPGA.
Key word: Digital audio frequency broadcast (DAB) channel coding FPGA
1 digital audio frequency broadcast (DAB) launching system and channel encoder
DAB is broadcasts the system after the amplitude modulation and the FM broadcast third generation. Compares it with the simulation broadcast not only to be possible to provide the high grade sound signal (the CD acoustic fidelity), may also provide the data, the image and so on many kinds of other accessorial services. It may protect in the high speed motion receive time the sound quality, has the very strong antijamming ability, in with wants under the petal bandwidth and the environment, DAB may provide the high grade many and varied broadcast program.
The DAB launching system mainly includes is in the program provider position the source encoder, is in the broadcasting station to develop the room position the multiple connection and is in transmitter internal COFDM (code Orthogonal Frequency Division Multiplexing) to code the modulator. And COFDM may divide into the channel coding, the OFDM well distributed digit the frequency conversion. This article main discussion uses FLEX10K series FPGA to realize the channel coding function.
The DAB channel coding part mainly includes the energy diffusion, the convolution to code and deletes, the time to interweave and so on, inputs to come from multiple connection’s ETI (service group transmission connection Ensemble Transport Interface) the frame, the output is the DAB transmission frame. Energy diffusion’s function is through causes the frequency spectrum proliferation to binary sequence randomisation processing, reduces the company ‘ 0 ‘ and the company ‘ 1 ‘ the appearance, protects the receiving end bit to restore on time. Regarding the signal transmission, because the convolution programming has introduced the massive redundancy bit, therefore the DAB channel coding uses the deletion convolution code. The DAB transmitter period of revolution interweaves the technology to correct sends arises suddenly square bamboo basket’s block mistake. It according to the rule which decides disrupts the data order of rank, causes in the channel Cheng Kuai the wrong dispersion in the different frame, recombination convolution code’s spot error correction ability, may cause according to receive machine can correct the block mistake which in the motion transmission appears frequently.
2 FLEX10K series characteristic
The FLEX10K series is one embedded programmable logical component which ALTERA Corporation produces (PLD-Programmable Logic DEVICE). FLEX (may change CMOS which logical unit array) uses may restructure the SRAM unit, its structure integrated has realized the complete characteristic which the general multi-purpose array needed. The FLEX10K series component capacity may reach 250,000, can the high velocity, the high performance the entire number system integration in the single component. The FLEX10K series’s high density and realizes easy in the design favors the function and the memory complex, enables its to be possible to adapt the system design request.
The FLEX10K component may II system develop through ALTERA MAX the PLUS, it has the formidable function, supports the schematic diagram, the hardware description language (VHDL, AHDL, verilogHDL) and so on many kinds of input modes. Realizes the DAB channel encoder with FPGA, simplified the system structure greatly. Moreover the VHDL description language’s use reduced the development time, strengthened system’s readability, is advantageous for the following product the promotion. If wants to change the software design, so long as the updated program, translates, downloading then, is very convenient. Even if must change the hardware design, may also through redistribute the FPGA management to realize, does not need the large-scale change original hardware. Looked from channel encoder’s function characteristic that majority is a bit operation. If uses DSP or Shan Shuiji, each instruction cycle can only process in a byte a bit, the efficiency is quite low. But FPGA might to many bit at the same time concurrent operations, enhance is an efficiency greatly. Because FPGA highest operating frequency above 100MHZ, therefore may through enhance FPGA the operating frequency to enhance it is the data speed.
In this design uses FLEX10K100A FPGA is in the FLEX10K series one kind, its equivalent gate number is 100,000, in constructs 24K byte RAM, the available I/O base pin achieves 289, core voltage 3.3V, supports the 5V input output. In the design uses the schematic diagram and the VHDL language mixed admission method.
3 use FPGA to realize the channel coding function
The DAB channel coding technology including the ETI solution multiple connection, the energy diffusion, the convolution code and the deletion and the time interweaves. And the ETI solution results in the multiple connection and the systems control realizes by piece of DSP ADSP2181, the hard core energy diffusion, the convolution code deletion time interweaves realizes completely by piece of FLEX10K100A. In a ETI frame mainly includes frame information (this and in frame various subchannels’ related information) and main service class data MST (including voice data symbol stream and fast data channel FIC). Figure 1 is the channel coding hardware realizes the schematic drawing. (ETI) meets the oral plate from multiple connection’s symbol stream after E1, solves the ETI frame, stores the input pair of mouth RAM buffer. When each (24ms) starts, the controller 2181 read in the ETI frame from the input buffer and calculates a group of control vector according to frame information, and writes it returns to input the buffer, then starts FPGA. FPGA first reads in the control vector, then acts according to its description to read in the ETI frame the MST territory various subchannels data to carry on the energy diffusion, the convolution to code and to delete processing which, the time interweaves, finally outputs the output buffer to give the OFDM modulator. And SRAM interweaves 16 data which the buffer uses for to deposit uses in interweaving.
Channel coding’s controller realizes by ADSP2181, control entire channel coding process complete movement, mainly includes start code module FPGA to start to code, controls FPGA from the exterior memory’s corresponding address read data, to provide for the code module carries on the complete parameter which, after the code the convolution code needs the data provides the memory address and so on.
The below detailed introduction realizes the channel coding process with FPGA. After DSP calculates the control information, starts FPGA. FPGA first reads in the computation obtained control vector the first several frame characteristic byte, had determined according to these bytes including the FIC channel’s subchannel integer and data-in’s start address, then reads in various subchannels characteristic byte separately, and carries on processing according to its description to various subchannels.
3.1 energy diffusions
The energy diffusion uses the schematic diagram input the method, realizes by 9 D triggers and the logical gate. In FPGA, first according to the byte read-in data, then carries on and/the string transforms, the serial input symbol stream and the production multinomial is P(x)=x9 x5 1, the original state entire ‘ 1 ‘ a pseudo-random bit sequence (PRBS) mold two adding together (processing order is the serial input 0th bit with the PRBS sequence 0th compared to special or), obtains the energy diffusion output symbol stream. Will output the serial symbol stream sends in convolutes the encoder. Figure 2 is the energy diffusion realizes the schematic diagram.
3.2 convolution codes
Convolutes the encoder also to use the schematic diagram input the method, as shown in Figure 3, realizes through the shift register and its different tap’s combination. Register’s initialization condition for entire ‘ 0 ‘, will input a bit to produce 4 bits every time to produce. When the valid data delivers, but must continue to send in 6 ‘ 0 ‘ to cause the complete register reset. If input length I sequence
, then the output sequence is
. The output sequence may also be represented as U=(u0, u1, u2,…, u4I 23), ui=xR(i/4), Q (i/4) (i=0,1,2,…,4I 23), R, Q respectively are the i/4 complement and business.
3.3 convolution code deletion
Before a convolution code output’s, 4I bit is divided into the continual bit block, each 128 bits. Each is divided into 32 bits 4 subblocks, these 4 subblock use identical deletion pattern, deletes the pattern to decide by PI, Table 1 is deletes the pattern table the part. The convolution code’s output and in the deletion pattern table’s deletion vector V deals with, the bit which is left over presses in a storehouse. When in 16 bits storehouses piles up when the bit counts >8, the encoder will delete the result to output according to the byte to 16 lengths interweaves the buffer interim. Primary data’s read-, the energy diffusion, the convolution code and the deletion are simultaneously carry on. When a sub-channel (or FIC) when the data reads off, the energy diffusion also stops, but the code and the deletion do not stop, but must carry on the final 24 bits codes and the deletion, these 24 bit use’s deletion vector VT= (1100 1100 1100 1100 1100 1100) carries on the deletion. Also regarding has the packing byte (Pad) must join the packing, a final output byte. PI is according to the input symbol stream bit rate, the protection level (P) and the guard mode (EEP/UEP) decides. In UEP (non-balanced error protection), (some sub-channel) divides into the entire frame’s symbol stream 3 or 4 (L1~L4), then on table look-up namely engineer should block PI and a packing bit number. Table 2 are this protection level pattern table part. Regarding EEP (balanced error protection), has A and the B two kind of protected mode table, respectively corresponds the input code rate is the 8Kbits/s integral multiple and the 32Kbits/s integral multiple, each sub-channel divides into 2. Deletion processing generally is carries on through the table look-up, but here table look-up’s work completes by the controller, in table look-up result existence control vector byte. FPGA may act according to the result code directly, reduced the FPGA order of complexity effectively.
3.4 time interweave
Interweaves when starts, FPGA already convoluted the result order which the code deletes to read in interweaves the buffer, then according to interweaves the rule chaotic foreword readout, completes the interweaving depth is 16 time interweaves. This buffer is piece of capacity 128K byte SRAM, divides into 16 8K the blocks, each block uses for to save a convolution code result. The SRAM address organization like chart 4 (in parenthesis is each frame start address). Table 3 show interweaves the rule to correspond in 128K interweaves the buffer, r is inputs the frame the serial number, r’shi the output frame’s serial number, i expression bit serial number, R (i/16) expressed that i divides 16 complements, r’(r, i) indicated outputs the r’zheng Ith bit to correspond outputs the rth ith bit. Ram_addr indicated that interweaves the buffer this frame start address.
Element form which modulator needs for mark DAB the launching system subordinate OFDM, after interweaving the result reads when the output pair of mouth RAM buffer according to the byte to conform to the transmission frame construction of data. According to the DAB transmission frame’s request, here output buffer may hold 4 logical frames the data, it selects patches or strips of land as worth saving for seed logic is also each 96ms changes one time, outputs in the RAM buffer construction of data like chart 5.
As stated above, the DAB channel encoder may (ADSP2181 make controller) by monolithic FLEX10K series FPGA to realize completely. This method easy to realize, the work to be stable, the speed quick, easy to promote, may take from now on the integrated special-purpose ASIC chip development core technologies foundation.
