The abstract union software radio the thought that proposed one kind based on the high speed transmission technology OFDM system design plan, including hardware constitution and system design realization; Has constructed an general hardware platform, may realize the high speed multi-carriers and the conventional single carrier modulation demodulation in this platform.
Key word Orthogonal Frequency Division Multiplexing (OFDM) DSP FPGA DDS DDC
Introduction
The software radio (Software Radios) is one kind of new radio traffic architecture. Specifically speaking, the software radio is take Yamagimachi programming DSP or CPU as the center, modular, the standardized hardware unit will connect with the main line way, constitutes the general hardware platform, and realizes each kind of wireless communication function open style architecture through the software load.
Along with correspondence development. The high speed transmission technology causes the extensive research and the attention. So far, the wireless transmission’s speed is restricted in the hardware condition. Must realize the high speed transmission, must unify each kind of chip the characteristic, enables the hardware platform to have, the general characteristic simply, therefore needs to develop an general platform.
DSP is controlling and the signal processing aspect has the superiority, operations and so on baseband signal modulation, demodulation and FFT/IFFT may realize by DSP, but receives the existing DSP processing speed and ability restriction in the real-time processing aspect. Arises suddenly regarding the signal examines this kind of operand big processing, particularly when high speed transmission, usually must use FPGA. Around the FPGA unique assembly line design structure may cause the level in the time concurrent, achieves is highly effective, is high speed. In order to reduce DSP in the signal processing pressure. Simultaneously satisfies the high speed request, uses the special-purpose digital frequency conversion chip to realize the digital high and low frequency conversion.
For with software radio thought unification, when system design considered that the compatible single carrier modulation demodulation way, uses DSP, FPGA, the high and low frequency changer’s plan, does not use the special-purpose modulation demodulation chip.
1 OFDM principle and baseband signal model
Orthogonal Frequency Division Multiplexing OFDM (Orthogonal Frequency Divi-sion Multiplex) is more than one carrier modulation system, through reduces and eliminates the code the crosstalk influence to overcome channel’s frequency selectivity decline. Its basic principle is the signal split is N sub-signal, then modulates N mutual orthogonal separately with N sub-signal the sub-carrier. Because the sub-carrier’s frequency spectrum overlaps mutually, thus may obtain the high frequency spectrum efficiency. In recent years OFDM obtained the widespread application in the wireless communication domain.
When the modulation signal arrives at the receiving end through the wireless channel, because the channel multi-diameter effect brings the code asked that the crosstalk the function, between the sub-carrier no longer maintains the good orthogonal condition, thus before transmitting, needs to insert the protection gap in the element between. If the protection gap is bigger than the biggest latency to expand, then all latencies are smaller than the protection gap’s multi-diameter signal will not extend to next element period, thus effectively eliminated the code the crosstalk. When uses the single carrier modulation, is reduces ISI the influence, needs to use the multistage balancers, this will meet restraining and the complex higher question.
Figure 1 is the OFDM baseband signal processing schematic diagram. And, Figure 1(a) is the transmitter principle of work, chart l(b) is the receiver principle of work.
In the transmitting end, first carries on QAM or the QPSK modulation to a bit class, then in turn and transforms and the IFFT transformation after the string, transforms again the parallel data as the serial data, in addition protects the gap (saying that “circulation prefix”), forms the 0FDM element. When group frame, must join the synchronized sequence and the channel estimate sequence, so that the receiving end can carry on arises suddenly the siberian elm to measure that the synchronization and the channel estimated that final output orthogonal baseband signal.
When the receiver examines the signal arrives, first carries on the synchronization and the channel estimate. When completes asked after synchronized, small several fold frequency offset estimate and correction, undergoes the FFT transformation, carries on the integral multiple frequency offset estimate and the correction, this time obtains the data was QAM or QPSK has adjusted the data. Carries on the corresponding demodulation to this data, may obtain a bit class.
Here only discusses the software function module, the concrete algorithm does not involve in this.
2 hardware architectures
The OFDM modulation demodulation and the conventional modulation demodulation compares, needs the operand is big, when particularly the system selects when the sub-carrier integer are many, the time which needs in the transmitting end IFFT transformation and receiving end’s FFT transformation is very only long. Usually uses FPGA and high speed DSP solves this problem. Because must complete the signal in the receiving end to arise suddenly digital signal processings and so on examination, synchronization and frequency offset adjustment, therefore the receiving end is higher to the timely request. In this system, uses FPGA to complete the signal to arise suddenly the examination and fixed time, DSP completes the FFT/IFFT transformation and the QAM/QPSK modulation demodulation.
This system abundant must be composed of 4 parts: DSP, FPGA, in orthogonal digit frequency changer (Quadrature Digital Upconverter), under orthogonal digit frequency changer (Quadrature Digital Downconverter). System hardware structure as shown in Figure 2. In the chart, D expresses the data bus, A expresses the address bus, C expresses the control bus, L expresses the chain street intersection data line, the letter following digital presentation main line’s figure. 50 MHz crystal oscillators are two piece of DSP and FPGA provide the clock signal, 32.768 MHz high stabilities inspire are AD9857 and AD6654 provide the high-grade most clock signal. Replacement chip MAX6708 controls DSP, FPGA, AD9857, AD6654 and the STl6C550 replacement.
DSP completes QAM or the QPSK modulation demodulation and the FFT/IFFT transformation. The system uses DSP is ADI Corporation’s Tiger sharcTSlOl. This DSP has the following characteristic: The highest operating frequency is the 300MHz,3.3ns instruction cycle; 6MB internal SRAM; 2 computation modules, each module has 1 ALU, 1 multiplier, 1 shift register and 1 register group; 2 trueing ALU, uses for to provide the addressing and the indicator operation; 14 DMA controllers; 1149.1 IEEE JTAG mouth. Regarding 0FDM baseband processing, this DSP most major characteristic is: Carries on 256 spots the plural number FFT transformations, only needs 3.67μs.
In the orthogonal digit the frequency changer uses ADI Corporation’s AD9857. The AD9857 highest operating frequency is 200 MHz, the output intermediate frequency frequency range is 0~80 MHz; Internal integrates half belt filter, CIC (CascadedIntegrator Cornb) the filter, the counter-SINC filter and the high speed 14 figure/mold switch, its core is phase continual direct digit frequency synthesizer DDS (Direct Digital Synthesizcr). In this plan, the AD9857 work in the quadrature modulation pattern, its 32 frequency control word causes the output frequency the most high precision is: SYSCLK (system clock) divides 2.
Under the orthogonal digit the frequency changer uses ADI Corporation’s AD6654. AD6654 internal integrated one 14, 92.1 6Msps mold/number switch and under 4/6 channel’s digit the frequency changer. Each channel may dispose independently. Under the digit the frequency conversion interior integrated the frequency converter, programmable cascade honeycomb filter (CIC), 2 filter group and the digit automatic gain control. And: The frequency transformation is realizes through 32 numerical control oscillators; CIC realizes 1~32 time of extractions; 2 filter groups including the FIR filter and 2 time of extraction half belt filter. Input intermediate frequency simulated signal after ADC and frequency transformation, uses the filter group to carry on the filter and the extraction, finally the parallel output orthogonal baseband digital signal, the input intermediate frequency signaling frequency is highest may arrive at 200MHz, this time, the use owes the sampling technique.
3 parameter designs and modulation signal profile
The author uses the PCB eight plywood designs, has realized this system’s hardware platform, and has realized the high speed OFDM transmission and the conventional single carrier modulation demodulation in this platform foundation, formed an general wide band high speed modulation to demodulate the platform. The design goal is must realize the existing complete physical level algorithm in this platform, specially realizes the real-time OFDM transmission system. Target request like table l which proposed to the OFDM system arranges in order.
Figure 3 gave 32 pathway carrier OFDM to adjust the waveform under the above parameter design (to see Figure 3(a)) and the power spectrum (sees Figure 3(b)). Attempts the neutron carrier modulation system is QPSK, the code high-rising frequency for the intermediate frequency frequency 36.864 other, the digital modulation way’s element frequency may reach 2MHz (i.e. regarding the four-phase modulation, a bit speed may reach 4Mbp; Regarding the 32QAM modulation, a bit speed may reach 10 Mbps), and sub-carrier modulation system, bit (or element) speed, output intermediate frequency adjustable.
4 conclusions
This article proposed the plan has the following characteristic:
①Based on double DSP structure. May work in the duplex mode, simultaneously completes the signal the launch and the receive; Work when the TDMA way or half-duplex, DSP may carry on the high-speed service through the Link mouth, is advantageous in the parallel processing, raises the transmission speed. DSP favors the baseband signal the real-time processing, may realize the high speed modulation demodulation.
②The frequency changer has the frequency resolution to be high, the frequency shift speed is quick, phase continuously, characteristics and so on easy numerical control. Uses DSP and frequency changer’s plan, not only may realize the analog modulation demodulation, moreover may realize each kind of digital modulation demodulation, compatible traditional modulation demodulation and new modulation demodulation way. MHz, the band width is 2.048 MHz. Figure 4 has given one kind of single carrier modulation service pattern (take π/4-QPSK as example) the time domain profile (sees Figure 4(a)) and the power spectrum (sees Figure 4(b)).
③Uses FPGA between DSP and the frequency changer, realizes arises suddenly the signal the synchronized capture, may share DSP the partial duties, thus enhances system’s timeliness.
