Abstract brief introduction tradition MVB communication controller chip MVBC structure and function; Through the deep research MVB first floor communication protocol, designs conforms to the IEC-61375 standard to use in the network connections the MVB main line visiting IP (Intellectual Property) the nucleus; Based on SOPC design concept. Integrated 32 NiosII soft nuclear processors and the MVB main line using SOPC Builder on piece of FPGA visits the IP nucleus, as well as some essential periphery module, and gives the MVB controller’s design to realize the plan.
Key word multi-purpose vehicles main line (MVB) MVBC the SOPC main line visits the IP nucleus
Introduction
Based on distributional control’s MVB (multi-purpose vehicles main lines) are IEC61375-l(1999) TCN (train communication network international standard) the recommendation plan, it the train correspondence main line which (stranded wire type train main line) constitutes with WTB has timeliness to be strong, reliable high characteristic. The train vehicles’ modernization trend of development and the reliability, the security, the correspondence timely request, cause MVB to become the next generation vehicles’ correspondence main line standard gradually. MVB takes the main line which the fast process control optimizes, can provide the best speed of response. Is mainly uses in having the interoperability and between the interchangeable request interconnection equipment’s serial data correspondence main line, suitable to serve as the vehicles main line, regarding the fixed grouping train, MVB may also serve as the train main line, as shown in Figure 1.
Along with system integration technology unceasingly mature, presented one emerging industry, namely IP (Intellcctual Property, intellectual property rights) product and modular design. In the integrated circuit design, the IP referring in particular to may through the intellectual property rights trade, circulate in each design company between realizes the specific function electric circuit module. The IP nucleus presents the nature characteristic is may the hawk use the nature, usually satisfies the good versatility, the probability and the absolutely correct 3 essential features, will be future SOPC (System OnProgrammable Chit))Design core. Must make SOPC to design successfully, must more use the intellectual property rights (IP) multiplying, by completes the design fast, obtains the low in price the silicon component, thus satisfies the market demand.
The author as well as the MVB first floor communication protocol has conducted the thorough research to overseas traditional MVB communication controller chip MVBC, based on this designed the proprietary intellectual property rights MVB main line to visit the IP nucleus, and using SOPC technical design MVB controller.
1 MVBC introduction
MVBC (multi-purpose vehicles bus control unit) is on the MVB main line’s new generation core processor. Its independence in the physical level and the function equipment, provides the correspondence connection and the communication services for main line’s on each equipment. MVBC and previous generation MVB communication controller BAP15-2/3 compares, had the very big enhancement in the performance, is on the present MVH main line the most advanced communication controller. MVBC internal structure as shown in Figure 2.
MVBC will use in coming from the MVB main line’s serial bit signal conversion for the parallel data byte, the byte junction which must transmit from the serial electric circuit transmits to the transmission medium on, will realize the data link layer as well as the part transmission level data processing, and will be interactive through the correspondence memory and the upper formation software. The bus control unit interior contains arranges the logic circuit which the demoding circuit and the control correspondence memory needs, uses for to control the frame the transmission and the receive (for example collision detection, a frame leader bit processing and CRC verification position processing and so on).
2 MVB main lines visit the IP nucleus realization
The main line visits the IP nucleus to use in replacing existing MVB network card’s MVBC chip to realize the application function, from the IP nucleus union physics level’s main line transceiver completes the main line visit. The main line visits the IP endorse to divide into the physical level, the data link layer and with the application layer connection 3 parts.
①Physical level: Realizes baseband Manchester Biphase-L to arrange the decoding, medium redundancy processing, the medium installs the unit interface, as well as uses in inputting the decoding the digital phase-locked loop design.
②Data link layer: Including addressing system, F-code (function code) production, main from equipment frame content packing as well as medium access control (MAC) and so on.
③With application layer connection: Usually uses shared buffer memory’s method, needs to complete port’s definition and the maintenance, the correspondence memory’s control and so on, its functional block diagram as shown in Figure 3.
2.1 MVB frame structure
Has two kind of frame forms in MVB: One kind is can only the main equipment frame which transmits by the main line main equipment, the abbreviation “the main frame”; Another kind is to respond the main frame, but by transmits from the equipment from the equipment frame, abbreviation “from frame”. A frame starts by 9 delimiters, main equipment frame dividing line Fu Hecong the equipment frame dividing line symbol regarding prevents the synchronized defeat is not same. Figure 4 is MVB main from the frame structure drawing.
2.2 MVB frame transmitter
The MVB main line data take the frame as the Fundamental unit, the data frame has used Manchester code transmission. Not only the encoder and the decoder will carry on Manchester to arrange the decoding, the frame frame tail arrange the decoding also to need specially to carry on here, use traditional Manchester codec encoder-decoder to be unable to complete this work. In this design, uses the union transceiver the state machine concrete condition to carry on arranges the decoding to suppose obituary the method to solve this problem. The MVB frame transmitter through the control logic module, transfers Manchester to code and the CRC verification module, the correspondence memory cell module completes the buffer data the transmission.
Following explains transmitter’s state machine FSM (Finite State Machine) design. A transmitter’s major function is realizes and the string transformation and the group frame. The MVB main line data after receiving the transmission setting signal starts to carry on the data transmission; After the data stores the correspondence memory cell, waiting control logic module setting signal; Then enters the frame the transmission mode, completes the shift which through clock signal’s triggering each condition asked that realizes a group of effective frame data transmission. Transmitter’s state machine FSM as shown in Figure 5.
2.3 MVB frame receiver
The receiver realizes the key is the valid data frame recognition, realizes the mentality to be similar to the transmitter, may realize according to the code verification. Another question is with main line’s connection way, this design has used 8 bit parallel data width output, adds serial number marking the method to be possible to receive assigns the length willfully the valid data. Receiver’s state machine as shown in Figure 6.
2.4 Avalon bus interface
Uses on the Avalon interactive piece which Altera Corporation develops the system bus to take this main line to visit the IP nucleus the internal integration main line, connects the IP intranuclear each module. As shown in Figure 7, the main line visits the IP nuclear structure to include: The encoder module, the decoder module, sleep the port refurbishing time monitoring module, a kind of equipment logical control module. The main line visits IP intranuclear to altogether have 4 Avalon from the port, on the NiosII master-control unit has established a Avalon main line main port, above other each module has established the Avalon main line from the port, realizes each module joint operation by the master-control unit control bus’s on data stream transmission, its functional block diagram as shown in Figure 7.
On 3 SOPC pieces system MVB controller design
3.1 main lines visit the IP nucleus and the NiosII system integration
Using QuartersII SOPC the Builder tool, integrated 1 32 NiosII soft nuclear processor, 4 KB internal RAM, the MVB main line to visit the IP nucleus (including encoder and decoder) as well as the LCD control module, constituted one on Altera CycloneII FPGA to be able to realize on a MVB kind of node function piece the system, as shown in Figure 8. Figure 9 is in SOPCBuilder each functional module withering with the situation.
On 3.2 NiosII processor’s software design
Based on the above SOPC system, has designed a basic MVB node, realizes the process data transmission. This node establishes the Oxl4 address as the source port. When main frame polling 0×14 address, this node packs Cheng Congzheng this port’s in data to transmit to the main line above, sleeps the port by the refurbishing 0×14 address.
MVB the mold physique document altera_avalon_mvb.h design, visits the IP nuclear register read-write including the main line the great definition.
Sets at the MVB main line receive permission position in the main function, the circulation waited for that receives main frame which the MVB master-control unit sends. The node after receiving the main frame, the procedure enters the interrupt handling routine. In the turban breaks in the main frame port address which in the procedure withdraws receives, and carries on the comparison with own preinstall’s end several addresses. If address match case, then the node sends to this port’s data through the MVB transmitter on the main line, realizes the port data refurbishing operation.
Main loop code selection:
4 simulations and actual profile
4.1 simulation profiles
In this experiment, has carried on the function simulation and the FPGA confirmation to the laboratory design’s MVB board card. Through has confirmed the MVB system which to process data’s transmission and the receive builds. To the MVB bus control unit sending process’s host from frame simulation result as shown in Figure 10. The transmission host from the frame data is 0×0055, contains 1 frame and 8 CRC verification data.
4.2 actual profiles
After composing the procedure, a recompilation QuartersII project document, will obtain .pof article assorted downloading to FPGA. After on electricity, measures the output pin with the oscilloscope, then may observe MVB from the frame profile, actual profile as shown in Figure 11. Compares the IEC-61375 protocol standard, may judge should cross the shape for the meet standards correct profile, and in the source port node has received the correct data, thus proves this process data port success refurbishing.
Conclusion
Because the MVB applicable scope, the supplier, the efficiency were inferior that several other kind of general field bus, possesses particularly with the MVB connection equipment needs to visit MVB through the MVB network interface unit, but the overseas company for this network card’s core chip - - MVB the communication controller chip MVBC monopoly, used this standard and the development for the domestic locomotive promotion has brought the enormous difficulty based on this standard other applications. At the same time, because at that time the fabrication technology and design technique’s limit caused the MVB network card to realize the method to be too complex, the construction cost was high. Therefore, the design proprietary intellectual property rights’s MVB main line visits the IP nucleus, has the practical significance very much. At present, the MVB controller has realized in the laboratory environment the procedure variable correct receive and the transmission. This main line visits the function which and MVBC the IP nucleus realizes quite, but because has used the advanced SOPC design technique, its architecture big simplification, the design difficulty also greatly reduces, had the very big enhancement in the versatile aspects.
