IP (Intellectual Propcrty) is the intellectual property rights which often said. The American Dataquest Consultant firm defines semiconductor industry’s IP to use in ASIC, ASSP and PLD in the middle and so on, and is the preliminary design good electric circuit module. The IP nuclear module has behavior (Behavior), structure (Structure) and the physical (Physical)_ three level of varying degree designs. According to the description function behavior’s difference, the IP nucleus divides into three kinds. Namely the soft nucleus (Soft IP Corc), completes the structure description the solid nucleus (Firm IP Core) and describes and undergoes the craft confirmation based on physics the hard core (Hard IP Core). The IP soft nucleus usually is presents the form submission with the HDL article to give the user, it undergoes the RTL level design optimization and the function confirmation, but does not include any concrete physical information. According to the above, the user may synthesize the correct gate level to suppose the scheme of entrapment table, and may carry on the following structural design, has the very big flexibility; With the aid of may synthesize a body very easily in the EDA synthesis tool with other external logic electric circuit, according to each kind of different semiconductor craft, designs has the different performance component. This article uses the advanced EDA software, uses the modulation design method from the top with the VHDL hardware description language, completed had the foreword auto-adapted function double pulse digit phase shifting trigger’s IP soft nucleus design.
1 three all control the bridge leveling circuit
As shown in Figure 1, three all control the bridge rectified current route 6 thyristor compositions. The common cathode group side and altogether positive level group side’s each 3 thyristors exchange the class, obtains in power source’s one cycle 6 times trades the class the pulsation profile. Three all control the bridge leveling circuit while any time must guarantee that has two different category thyristors the breakover to be able to constitute the return route. Trades the class only to carry on this group, every other 120° trades class one time. Because altogether the cloudy level group trades the flow point great distance with altogether the positive level group 60°, therefore every other 60° has a part to trade the class. The group in various thyristors’ trigger pulse phase difference for 120°, meets in the identical two part’s trigger pulse phase difference for 180°, but the neighboring two pulse’s phase difference is 60°.
2 IP soft nucleus design
2.1 trigger pulse output design mentality
This design’s trigger pulse phase shifting is take three natural phase change as the datum, three power source U, V, W input will undergo 22 cancellations and the rectification later obtains the cycle will be 20 ms, the phase difference for 120° three group square-wave A, B, C (as shown in Figure 2), will take the top layer module the lock input. The analysis trigger pulse may discover, no matter the phase shifting triggering angle for how many, by a zero crossing achievement synchronization spot, starts from the synchronized spot one cycle 360°, produces 6 output pulses inevitably. This design uses the double narrow pulse, each time two groups outputs. 6 thyristor’s triggering by A, B, in the C plus and minus level cycle carry on the time delay separately. For example: In a level cycle, take a rise along as an initial station, passes through after the phase shifting angle decision time delay, sends out VTl the trigger pulse; In the double narrow pulse application, simultaneously sends out VT6 the trigger pulse. Trigger pulse succession chart like chart 3 dawn shows.
May realize starts from the natural phase change spot 0°~180° the time delay, the design mentality simply direct-viewing, but usually designs must differentiate the different phase shifting scope. When external input 6MHz clock, may realize the precision for O.003° the phase shifting, meanwhile may realize the foreword to be auto-adapted.
2.2 IP soft nucleus design mentality
Uses the hierarchization to suppose the juice thought that divides into the top layer module and the submodule the module, various modules use the VHDL language to carry on the design. Top layer module (Trigger) decides the entire design the input/output interface and each submodule connection relations. The design mentality is: The phase shifting angle input by the parallel 16 bit data line input, and preserves in the phase shifting angle register; A, B, C three input takes the phase shifting triggering output the datum, carries on the time delay according to the phase shifting angle register’s in time delay value to the corresponding thyristor’s trigger pulse; The trigger pulse outputs by VTl~VT6, CLK is the clock input, SOUT is the cycle is the 3.3ms synchronized output. Altogether has 4 sub-module s_pulse, ph_adp, delayer and word.
the s_pulse module A, B, C_ three inputs through the D trigger realizes the clock synchronization, enables by the TAF_EN signal input as the phase shifting angle renewal. When TAF_EN is 1, with parallel l6 in bit data mouth D0~D15 data updating phase shifting angle register’s value.
the ph_adp module according to A, B, C three inputs completes the foreword judgment. Foreword judgment based on the below algorithm; When A (U-V) rise along arrival, if A, B, C three input the level is 101, for the positive phase sequence (U, V, W) inputs; If A, B, C three input the level is 110, for the negative phase sequence (U, W, V) inputs. Module output signal ps, ns take, the negative phase sequence symbol separately.
the delayer module has the width is the O.8 ms trigger pulse. Trigger pulse’s production respectively take the rise which, the drop three input along as a datum, according to the phase shifting angle register’s in value, completes 6 trigger pulses by the CLK triggering counter the time delay. For example: Take the lock input A rise along as the datum, starts by the CLK flip-flop number to count, when after the counting value achieves in the phase shifting angle register’s value, sends out a width is 0.8 ms trigger pulse VTl; Three input the rise, the drop along use the respective counter separately.
the word module completes the trigger pulse the modulation. The modulation frequency is 10 kHz, enables in each trigger pulse to have 8 sub-pulses, controls extremely through the pulse transformer to 6 thyristor’s gates, and according to the foreword symbolized that ps, ns send out the trigger pulse by the correct order.
Time the positive phase sequence trigger pulse order is: VTl→VT2→VT3→VT4→VT5→VT6→VTl.
Time the negative phase sequence trigger pulse order is: VT6→V15→VT4→VT3→VT2→VT1→VT6.
2.3 IP soft nucleus design realizes
In this design, the IP soft nucleus realizes by the VHDL language compilation, uses synplicity Corporation’s Synplify Pro to complete the translation and the synthesis. Synthesizes later RTL level system diagram as shown in Figure 4.
May act according to the different component which the concrete system uses to carry on the synthesis, uses the different component manufacturer the layout wiring tool to produce the programming document again, then downloads concretely to assorted, completed this IP soft nucleus application to realize.
3 IP soft nucleus simulation and confirmation
In order to confirm this IP soft nucleus the logical function, needs to carry on the function simulation to it. Compiles testbench, carries on the functional module in simulation software Modelsim to the top layer module. Uses testbench to be possible for the functional module which designs to carry on the nimble simulation, examines the IP soft nucleus, time the negative phase sequence input as well as each kind of phase shifting angle output to be whether correct. Figure 5 and Figure 6 respectively be, negative phase sequence input when phase shifting angle for 120° simulation profile.
May see by the simulation result, this IP nucleus’s logical function is correct. Carries on the translation after QuARTUSII, downloads to Altera Corporation’s new generation CPLDMAXII series EPMl270, can realize the precise phase shifting as well as the foreword is auto-adapted.
4 conclusions
According to the IP soft nucleus’s design cycle, has completed the entire digital 22 thyristor phase shifting trigger’s design. This method has solved the different phase shifting scope trigger pulse output problem, and realized the foreword to be auto-adapted, was three thyristor phase shifting triggering circuit’s application provides effectively has been possible the multiplying design method, caused the entire control system’s design to be able to simplify. This IP soft nucleus’s design has succeeded applies in based on the TMS320LF2407A direct current machine velocity modulation system.
