Abstract: This article introduced the high speed magnetism floats in the train to measure the fast localization unit and the vehicle carry between equipment’s correspondence request, and proposed take this as the foundation one kind realizes the method based on the RS485 physics level synchronous communication. Uses Xilinx Corporation XC2S100 to take the correspondence transceiver, uses TI Corporation TMS320F2812 to take the communication controller, has worked out the system software and hardware design proposal, and through simulation and experimental verification this plan in practical application feasibility.
Key word: Magnetism floats the train; RS-485; Synchronous communication
In the high speed magnetism floats in the transportation system, Che Zaice the fast localization unit carries on the real-time measurement to vehicles’ position and the speed, and the position and the rate signal through the radio system transmission to the ground in draft control system and the operating control system, uses in the reaction control which the long stator straight line synchronous machine tows, as well as vehicles movement direction and safety protection. Measured that the fast localization unit is the hauling and transports controls the system closed-loop control the core and the key.
Measured that the fast localization unit close neighbor aerosol electro-magnet and the long stator winding and the iron core, are in the aerosol magnetic field and tow in the magnetic field, the electromagnetic environment is complex, this set the very high request to its communication facility’s electromagnetic compatibility performance. Moreover, to meet the draft control system’s need, measured that the fast framing signal the accuracy requirement is quite high. Therefore, measured that the fast framing signal transmission the speed, timeliness and the reliability face the challenge. Based on the above consideration, this article proposed floats the train synchronization 485 mailing addresss based on DSP and the FPGA magnetism the research, solves the above challenge.
Synchronization 485 realizes the method
Considered measures the fast localization unit the working conditions and the correspondence function demand, when chooses this unit and the vehicle carry between the radio system’s mailing address, the process analyzes, this research has selected the transmission speed high synchronous communication method, and uses the shielding properties good twisted pair line to realize the RS-485 balanced type difference transmission.
Connection design and communication protocol
Measured that the fast localization unit and the vehicle carry between the radio control unit correspondence connection relations as shown in Figure 1. The vehicle carries the radio control unit prosecution, the vehicles measured primarily fast to receive the prosecution with the localization unit. Correspondence both sides by the transceiver and the controller constitution, between the transceiver select the RS-485 synchronization serial interface method, each connection has 4 pair of bad parting lines.
Figure 1 correspondence connection relations schematic drawing
In Figure 1, CLK is the clock signal, ANF is the radio request signal, UEF is the gating signal, DATA is the data signal. The vehicles measured that fast localization unit each 20ms transmits one time to the radio control unit the data, the transmission speed is 512kbps. In order to prevent the small signal impulse the disturbance, the ANF signal’s width is 10 CLK signals; After the ANF signal becomes the low level, waited for that 10 CLK signal width, UEF only then starts to jump effectively. ANF, UEF, DATA signal in CLK rise along change. When non-signaling, UEF, DATA, ANF are the low level, the clock signal maintain the transmissions. The data transmission selects the left shift method, namely passes on the top digit first, rear-drive low position. Information frame form as shown in Table 1.
Shows the information frame form
The synchronized 485 transceivers realize
In this article elaborates in the communications system, the vehicles measured that the fast localization unit and the vehicle carry radio control unit both sides to use XC2S100 to take the correspondence transceiver, the simulation synchronization 485 transmissions and the receive succession. The synchronized 485 FPGA designs are mainly based on the Verilog hardware description language, uses EDA tool including ISE (including its internal integration tool), Modelsim.
Clock and timing signal production
The vehicle carries the radio control unit to need the production rate is the 512k clock signal and 20ms a time ANF signal. Moreover, this unit when serial receive locator data receives the clock to be 512k (baudrate clock) 16 times, namely 8M. Therefore, the frequency divider obtains the effective application in the synchronization 485 mailing addresss.
To the even number frequency division, only need design a counter to carry on the counting, treats the counting to frequency division number 1/2:00, after causing the frequency division clock level turn over then; The odd number frequency division is more complex, because the counter cannot carry on the counting to the non-integer, must use certain algorithm to carry on processing. Here carries on the function simulation after the odd number frequency division module the profile see Figure 2.
Figure 2 frequency division module simulation model
ANF signal every other 20ms transmits one time, each time transmits the pulse width is 10 clock cycles. The ANF signal’s production may divide into two parts to realize: First produces is separated the 20ms signal impulse, then turns this signal impulse’s width 10 clock cycles.
Serial data transmission and receive
When has the serial data, according to communication protocol’s request, measured that fast localization unit every other 20ms should serial emigrate the 72bits data. If each transmission clock cycle emigrates, then needs 72 clock cycles to be able to emigrate, therefore the gating signal also needs to maintain 72 clock cycles the width.
When receives the serial data, the synchronization serial receives a (72bits) data and the asynchronous serial receive is different. Because receives and dispatches the clock is not asynchronous, therefore cannot judge the first low level which will appear in free time condition later to take a start, but along will take a data arrival by the gating signal (UEF) rise the judgment. In order to avoid in the data transmission process the burr influence, we still carried on the receive by baudrate clock’s 16 times, namely every other 16 baudrate clock cycle sampling one time, therefore, each data in transmission each center point place by sampling.
The serial data transmission and the receive simulation succession chart see Figure 3.
Figure 3 synchronized 485 simulation succession chart
Between transceiver and controller’s data exchange
Is simulates based on the RS-485 synchronous communication succession with FPGA as the correspondence transceiver, but the correspondence data is finally carries on the data exchange with system’s CPU. In this mailing address’s design, correspondence both sides use TMS320F2812 to take the communication controller. FPGA and the DSP data exchange must satisfy certain succession, can guarantee that measured the fast localization unit carries the radio control unit to the vehicle real-time to transmit the position and the rate signal. In this system, the DSP controller uses the C language to carry on the software design.
Measured that the fast localization unit leans DSP and the FPGA data exchange
TMS320F2812 exterior memory XINTF may supply the choice the exterior address space to have XINTF0, XINTF2 and XINTF6. And XINTF0 uses the XZCS0AND1 achievement to select patches or strips of land as worth saving for seed the signal, the exterior memory expands the space is 8K; XINTF2 and XINTF6 use XZCS2, the XZCS6AND7 achievement to select patches or strips of land as worth saving for seed the signal separately, the exterior memory expands the space is 0.5M. Measured the fast localization unit when transmits the position speed information, transmits FPGA, DSP through the DSP data line to act according to the corresponding exterior memory to select patches or strips of land as worth saving for seed the signal to discover corresponding the address, in obtains a new locator data after the first floor sensor reads in this address. Corresponds the hardware connection diagram see Figure 4.
Figure 4 the transceiver writes the data the hardware connection
According to the agreement request, locates the information each time transmits when including 5 byte user data and 2 byte CRC verification, therefore, the 16bits data line needs to transmit continuously at least four times, can transmit completely the first floor localization information FPGA.
In order to reduce the hard segment, here only connects the address wire high five, carries on 4~16 decodings to low four address wires, the highest order address wire takes this decoder to enable the signal. Takes corresponds in an exterior memory selects patches or strips of land as worth saving for seed the signal four addresses, for instance selects patches or strips of land as worth saving for seed signal XZCS2 is low, then selects 0 xe 0000,0 xe 4000,0 xe 8000,0 xec 4 addresses to write the data as DSP to FPGA the address.
Because each different address corresponds an address decoding value, when after four decoding values appear, only then may think that a localization information transmission completes. By now seven bytes which received continuously added on the frame and the frame tail, the achievement measured that the fast localization unit transmission carried the radio control unit for the vehicle a data.
The vehicle carries the radio control unit to lean DSP and the FPGA data exchange
In order to avoid taking the excessively many CPU resources, the vehicle carries in the radio control unit DSP reads when the data from FPGA not to select the inquiry method, but uses the external interrupt to receive the data. The DSP 16bits data line and the FPGA connection, DSP XINT1 also connects FPGA the I/O base pin. If selects XZCS0AND1 to take the exterior memory to select patches or strips of land as worth saving for seed the signal, then DSP reads the data from FPGA the addressing space scope is 0×002000-0×004000, in this address range reads out the data namely delivers DSP for the data line upload the locator data. Corresponds the hardware connection diagram see Figure 5.
Figure 5 the transceiver reads the data the hardware connection
Because FPGA transmits to a DSP data is 72bits, therefore needs through the 16bits data line transmission 5 times to be able to transmit, each 16bits data arrives when has an external interrupt. Supposes the baudrate clock is 512k, the supposition from a localization unit complete data is 0×02123456789abcde03, the vehicle carries the radio unit to retransmit through the 16bits data line to the DSP data is at different times 0×0002, 0×1234, 0×5678, 0×9abc and 0xde03. The data and the signal of stop produce succession as shown in Figure 6. May see by Figure 6, each correspondence emigrates one time dataout, can send out external interrupt signal xint1, DSP correspondingly, once receives the external interrupt, then in interrupt servicing subroutine from 16bits data line read signal value. For a complete receive signal, may define 16 level of FIFO in the external interrupt service routine, when from the FIFO lowest level read-out’s data is 0×02, then may judge a data the start (, if has 0×02 in user data and verification value, then must carry on corresponding character figurative meaning), receives the following data then to obtain a complete localization information in turn.
Figure 6 reads the data the simulation model
Correspondence both sides schematic diagram
485 realizes the method description according to above to the synchronization, uses the top layer schematic diagram like chart which in ISE the ECS tool describes 7 and shown in Figure 8. Including measured that the fast localization unit synchro data transmission and the vehicle carry the radio control unit synchro data to receive two parts.
In Figure 7, addr_decode is the address decoding module, uses in receiving a localization information completely from DSP; tra485data is the serial data and the gating signal transmission module. And, din(15:0) comes from DSP directly the 16bits data line; addr(3:0) and the DSP A17~A14 address wire is connected; clkin and the anfin signal carries the radio control unit by the vehicle to provide. Output dataout and uefout after output cushion and difference level switch gives the vehicle to carry the radio control unit.
Figure 7 synchro data transmit mode schematic diagram
In shown in Figure 8 Che in Zai the radio control unit synchro data receiving end’s schematic diagram, divide_512k is transmits the clock to have the module, produces baudrate clock which the message center needs; anf_shift uses in producing the radio request signal; rec485data uses in the serial receive localization information and retransmits through the dataconvert module to the communication controller. And, Dataout(15:0) arrives at the DSP, Xint1 company through the data line company to arrive at DSP directly the external interrupt 1. anfout and clkout after input crystal oscillator frequency frequency division obtains, after output cushion and difference level switch gives the vehicles to measure the fast localization unit.
Figure 8 synchro data receiving end schematic diagram
Conclusion
In the high speed magnetism floats in the train special traffic environment, manifests its anti-jamming based on the RS-485 physics level’s synchronous communication way to be strong, timeliness is good, error rate low status merit, and realizes the principle to be simple. The correspondence transceiver design which realizes using FPGA is flexible, the reliability is high, its function obtained the confirmation in the practical application.
Reference:
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