The Turbo code is under one kind of low signal-to-noise ratio condition can also achieve the outstanding error correction performance the channel coding. The early time to emphasize Turbo code close Shannon limits the outstanding performance, research symbol length very big [1~2], the existence decoding order of complexity is big, when decoding questions and so on extension. Arises suddenly the data communication to transmit the small length data message service primarily, therefore arises suddenly in the correspondence the Turbo code code length is also below the medium length. This article face arises suddenly in the data communication the channel coding application, studied the short frame size Turbo code to arrange the decoding algorithm FPGA to realize. Realized uses the optimization to arrange the decoding algorithm, reduced the decoding order of complexity and the decoding time delay. Finally the simulation and has tested the Turbo decoder’s error correction performance and the volume of goods handled.
1 Turbo code encoder’s FPGA realizes
The Turbo code’s encoder is (recursive system convolution code) the component encoder and one interweaves by two RSC is composed. Not only the RSC code has the systematic code merit, moreover regarding a RSC code, always has one to have the identical trellis work NSC code (non-system convolution code). In this system uses two same RSC encoders, the production multinomial is G=[1,15/13], the system encoding rate is 1/3.
Interweaves the function is combines using the randomisation thought two mutual independent cut numbers a long stochastic code. In this topic the Turbo code interweaves realization is constructs one to interweave the address generator, and according to the input frame size information, real-time produces interweaves the address sequence.
Figure 1 is encoder’s FPGA realizes the structure drawing. Before the code, the address generator gain frame size information, completes interweaves the address production preparation process. When code, the information sequence is read in turn pair of mouth RAM, after treating finished a data, the address producer starts to produce the sequence address and to interweave the address. Double mouth RAM X and interweaves the information sequence X’jinxing RSC code after two address read information sequence; Finally encoder output system position X and verification position P0 and P1.
2 Turbo code decoder’s FPGA realizes
The Turbo code decoder is quite complex, below from decoder’s connection, the internal structure, the internal sequential control, the component decodes the MAX-Log-MAP algorithm and the SISO module realizes five aspects to come to elaborate in detail decoder’s FPGA realizes.
2.1 decoder’s connections
Turbo code decoder top layer module’s connection base pin as shown in Table 1.
2.2 decoder’s internal structures
The Turbo code decoder by two soft input/soft output component decoder, interweaves as well as the corresponding solution interweaves the constitution. The decoding is the information between two component decoders the iterative computation process. In the iterative computation, the previous operation obtains uk outside information λe (uk) to take next time operates uk apriori information λa (uk). The Turbo code component decoder decoding algorithm mainly has the MAP kind (biggest probabilityaposteriori decoding algorithm) and the SOVA kind (decides Viterbi decoding algorithm softly) [3]. This article uses the operation order of complexity and the performance moderate MAX-Log-MAP algorithm. Turbo code decoder FPGA realizes internal structure as shown in Figure 2.
The address generator and the encoder are the same, use in the data interweaving the reconciliation to interweave. The data-in memory uses in saving the input the receive data, including system message sequence memory as well as each verification sequence memory. Outside the information-storing device uses in the outside information which saves the iterative decoding to produce. Because outside the information needs to take the next decoding the apriori information, therefore here outside information-storing device has two, saves two component decoder’s outside information alternately. SISO module namely for soft input, soft output component decoder. The entire Turbo code decoder has two SISO component decoding module. But to save the resources, this plan has only designed a SISO module, takes two component decoders the multiplying. In Figure 2, 
in expression receive symbol systematic position, in expression receive symbol verification position.
2.3 decoder internal sequential control
The Turbo code decoder internal sequential control completes by the state machine. The entire decode procedure divides into the initialization, the receive data storage, the iterative decoding and the hard decision outputs four processes, and corresponds to state machine’s INIT, STORAGE, SISO and the OUT four conditions. Decoder’s internal behavior shift as shown in Figure 3. Original state INIT completes initialization work and so on frame size hypothesis, and completes interweaves the address production preparation process, once instructed when first data feeds fd signal effective (high effective), enters the STORAGE condition; Condition STORAGE will complete will receive the data series to store in single mouth RAM, after treating a data finished, instructed the memory finished the rdyStr signal set high, entered the SISO condition; Under condition SISO, the SISO component decoder carries on the iterative decoding according to the hypothesis iterative number of times to the receive data. When iterates completes, rdySiso sets high, enters the OUT condition; Outputs to the data hard decision and counts, this time outputs desired signal ready to set high, after treating decided completely finishes, returns to the INIT condition.
2.4 component decoding algorithm - - MAX-Log-MAP algorithm
The MAP algorithm needs the massive multiply operation and the index operation as well as the massive memories, the operation is very complex. The Log-MAP algorithm transforms the MAP algorithm’s in multiply operation for (does not need to the number field additive operation logarithm operation), suits the project to realize. Therefore when the project realizes, may in transform originally to the number field additive operation to take two numbers big to add on a correction term the operation. If also abbreviates the correction term operation, then the Log-MAP algorithm may simplify is the MAX-Log-MAP algorithm. MAX-Log-MAP algorithm main computation step following [4~5]:
(1) calculates on the Turbo code code grid chart the branch way measure value:
Because Lc value to decoding performance influence not big [6], for the convenient fixed point realizes, in this article the simplification is Lc=1.
2.5 SISO module realization
Component decoder’s FPGA realizes the SISO module uses the modular design, mainly includes the forward measure computation module, the reverse measure computation and the logarithm likelihood ratio computation module, the forward measure memory as well as the normalized measure memory. Because the forward measure computation and the reverse measure computation need to calculate the branch measure, therefore may calculate and save the branch measure in advance. But in this plan, to save the storage space, has not carried on the memory to the branch measure, but in forward and reverse measure computation time calculates one time, moreover after reverse measure computation restraining simultaneously calculates the logarithm likelihood ratio.
Carries on with FPGA to the algorithm when the fixed point realizes, needs to consider the overflow the question. In order to prevent in the computational process to present the overflow, carries on normalized processing to the forward measure and the reverse measure computational process. If in some time normalized measure value choice current frequently forward measure maximum value, then the normalization is the forward measure and the reverse measure subtracts this maximum value. After the normalized forward measure and the reverse measure formula is as follows:
The SISO module internal treatment flow divides into the initialization, the forward measure to calculate and to save, the reverse measure computation and the logarithm likelihood value calculates three parts, and corresponds to state machine’s three condition INIT, FSM and RSM. SISO module’s internal succession as shown in Figure 4. The INIT condition completes the internal register’s initialization establishment, when external input signal Siso_start is effective, starts the SISO module, enters the FSM condition; In the FSM condition, in every 8 clock cycle, and type (2) calculates one time correspondence before type (1) 8 to the measure value, and chooses most greatly forward measure value to take the normalized measure value, calculates normalized after type (8) forward measure value. Starts a forward measure to write a letter the number, 8 which, before the memory current computation obtains to the measure value and the current normalized measure value. When all forward measure computation finished, started the Fsmrdy signal, entered the RSM condition; In every 10 clock cycle, and type (2) calculates one time correspondence with type (1) 8 reverse measure values, after type (9) computation normalization’s reverse measure value, and type (5) calculates the corresponding time with type (4) the logarithm likelihood ratio and outside the information logarithm likelihood ratio, and outside the information logarithm likelihood ratio will save. When all computations complete, starts the Rsmrdy signal, enters the INIT condition.
Because in this plan the SISO module takes the multiplying two component decoders, corresponds in a decoding iteration two-and-a-half iterative process. Therefore Figure 4 Decoder_num is when is low, the SISO module takes the first component decoder, carries on the first-and-a-half iterative computation; Decoder_num is when is high, the SISO module takes the second component decoder, carries on the second-and-a-half iterative computation. Each time half iteration produces the logarithm likelihood ratio information takes next time half iterative the apriori information. Saves the outside information logarithm likelihood ratio which with two RAM two-and-a-half times iterates produces. When first-and-a-half iterates, outside from the second outside information-storing device reads the outside information logarithm likelihood ratio which the previous -and-a-half times iterate produce to take the apriori information, after the computation obtains the information logarithm likelihood ratio, saves to the first outside information-storing device; When second-and-a-half iterates, outside from the first outside information-storing device reads the outside information logarithm likelihood ratio which the previous -and-a-half times iterate produce to take the apriori information, after the computation obtains the information logarithm likelihood ratio, saves to the second outside information-storing device. In each data decoding’s first iteration’s first-and-a-half iterates the apriori information supposes is 0.
After the iteration satisfies the iterative termination criterion, the decoder stops the iteration, decides the output decoding result hardly by information logarithm likelihood ratio. In the project the commonly used iterative termination criterion is the establishment biggest iteration number of times. The biggest iterative number of times’s hypothesis needs the overall evaluation error rate performance and the system volume of goods handled performance.
3 Turbo codes arrange decoder’s performance
The Turbo code which proposed based on above arranges decoder’s FPGA to realize the plan, this article in Xilinx Corporation’s Virtex2 series XC2V500-6fg256 on the FPGA chip, realized the frame size invariable Turbo to arrange the decoder between 64~1 024 scopes. The data-in 4bit quantification, the internal data bit wide chooses 12bit, the encoder module and the decoder module in realizes together with the FPGA chip on. After the synthesis, the clock most minor cycle is 7.188ns, the correspondence highest clock rate is 139.121MHz, occupies resources as shown in Table 2.
The detention and the volume of goods handled are weigh the decoder performance two major targets or quotas. The detention defines as from the first data feeds to the first data output time difference. The volume of goods handled defines the data quantity which can process for average each second. In the frame size is 1 024, iterative number of times is under 5 conditions, the decoder time delay approximately is 1.4ms, the volume of goods handled approximately is 0.72Mbps.
Finally, to the frame size was 128, 256, 512 and 1 244 kind of condition Turbo code decoders has carried on the error rate performance test. In the test system joins the white gaussian noise, the data uses the BPSK modulation, the decoder 5 iterations. Test result’s performance curve as shown in Figure 5. The test result indicated that in the signal-to-noise ratio is lower than 4dB under the condition, the frequency-hopping number passes on the communications system to use Turbo to arrange the decoding plan, the error rate is smaller than 10-5, has met the data transmission reliable requirements. Because decoder’s frame size in 64~1 024 scopes invariable, therefore very suitable to apply in arises suddenly in the data communication in the error control.
Reference
1 Berrou C, Glavieux A, Thitimajshima P. Near shannon limit error-correcting codeing and decoding: turbo codes. in Proc.ICC ‘ 93, Geneva, Switzerland, May. 1993:1064 ~1070
2 Berrou C. Near optimum error correcting coding and decoding-turbo-codes. IEEE Transcations On Communications, 1996; 44(10)
3 ten thousand flower buds. Turbo code and in third generation mobile communication system’s application. Beijing Institute of Technology doctorate paper, 2001
4 Robertson P, Villebrun E, Hoeher P.A comparison of optimal and suboptimal MAP decoding algorithms operation in the log domain. in Proc.ICC’95, Seattle, WA, June 1995:1009 ~1013
5 Liu Donghua. Turbo code principle and applied technology. Beijing: Electronics industry publishing house, 2004
6 Worm A, hoeher P, When N. Turbo-decoding without SNR estimation. IEEE Commmun,2000; (4):193~195
