Flows the piece success to be decided for the first time by the overall system hardware and the related software’s confirmation, some companies provide the fast prototype produces the platform to have many debugging functions, but these platform’s price is high.
Therefore the most popular procedure is according to DUT and the concrete application design compound FPGA board, confirms these boards the schematic diagram usually is very troublesome, this article proposed that one kind realizes the prototype board schematic diagram confirmation new method using FPGA.
Because the price competition is getting more and more intense, flows the piece success or only needs the few revisions becomes for the first time more and more important.
In order to achieve this goal, to overall system (i.e. hardware and related software) confirmation into the most important.
The field also emerged many strategies to help the designer to complete on RTL the software movement. These strategies have provided in the final hardware also when the fermentation develops software’s one way.
This measure perhaps also insufficient, the reason also has two: First, the simulation system possible and the actual system has the big difference; second, the systems operation speed is slow. Therefore may consider that the complete design will map in first FPGA, then moves the goal application procedure.
Does this possibly cannot achieve the final silicon chip’s conventional target, but may test the entire hardware’s function, the system can obtain the comprehensive confirmation, some test case possibly is unable in the simulation to complete radically. Moreover, may use in the holonomic system prototype which demonstrates before the silicon chip succeeds may arouse the customer interest well.
Some companies provide the fast prototype produces the platform to have many debugging functions. These circuit wafer platform has the programmable interconnection, may the FPGA peg grafting in above, and (is surveyed DUT idea) to map in these FPGA. But these platform’s price is high.
Therefore most popular procedure according to DUT and concrete application design compound FPGA board. Certainly, these boards similarly can also use in testing in the goal application the final silicon chip.
Confirms these boards the schematic diagram usually is very troublesome, because in the schematic diagram some small wrong serious influences to the design schedule.
The schematic diagram confirmation work is completes artificially, therefore the mistake is also unavoidable. If can the multiplying DUT confirmation environment confirmation circuit wafer schematic diagram, then the schematic diagram confirmation might apply. How will this article discuss and revises the DUT confirmation environment through the compilation few scripts to serve this purpose.
Chart 1:DUT by the x86 processor, the main span (Host Bridge), the SDRAM controller and the PCI bridge is composed
Method synopsis
The basic idea is tries to the schematic diagram to carry on the simulation. This has achieved this point, transforms the first schematic diagram network table the Verilog net table. On the circuit wafer installs the different part (for example FPGA, processor, the PCI card, SDRAM and so on) either use RTL to replace, either uses the behavioral model which in the RTL proof procedure uses to substitute. It is noteworthy that our already supposition entire design’s Verilog/VHDL code was ready-made. Needs to use in as for the circuit wafer on testing DUT the processor, SDRAM, the PCI component and so on other parts, also the supposition already had corresponding BFM (main line functional model)/the model. Because this stage is after the function confirmation, but these parts need to use for to test DUT, and simulates the overall system, therefore their equivalent behavioral model should already obtain the use in the function confirmation, now is only is redundant the use, crossed immediately little can use the same environment and test the case diligently.
Figure 2: Contains the x86 processor chip, 2 FPGA, SDRAM and 1 PCI mortise’s prototype board
The above concept may confirm the silicon chip after the development to live the forming the schematic diagram, the basic supposition is designs the team to have silicon chip’s HDL description. This is the main point is. Regarding the FPGA board, may the method which is accommodating through some kind dispose the FPGA pin to overcome, because in the schematic diagram wrong connection causes the question, namely the designer may manage and solve these mistakes. But used for regarding the preparation to test the final silicon chip’s board is nearly impossible.
Produces the Verilog net table
May use several kind of schematic diagram input tool to produce the Verilog net table. Based on the following several kind of limit reason, this kind of net table in fact cannot use:
1. it regards as board on each part is a module, therefore produces in the Verilog document contains all part’s example, like FPGA, the electric capacity, on pull the resistance or the crystal oscillator, no matter but these parts whether in Verilog modelling. And some parts (for example series connection resistance, decoupling electric capacity) may delete simply from the net table.
2. in the schematic diagram main line is usually connected on the mark each one pin, but the main line possibly has a port in the Verilog module. Therefore possibly does not have the one-to-one corresponding relationships. For example in the Verilog module a four output address bus by the statement will be: output [3:0] Address; But in the schematic diagram possesses these four pins is stated independently. This will cause in the mark pin output which and the Verilog module in the schematic diagram will use the corresponding mark available function is incompatible.
Therefore, the designer needs to compile a simple script, either revises this Verilog net table, either other forms which supports according to the schematic diagram input tool found a new net table. The goal is analog elements and so on deletion resistance, electric capacity, inductance, or replaces them with the equivalent Verilog code.
To realize this goal well, may use to analog element’s naming convention, or defines them in a document takes the script the input. For example, the resistance may by the naming be R1, R23 and so on, does not follow this naming convention the part to be possible to define in the restraint document, such script may be connected them the equivalent model, or the hypothesis short-circuits them removes from the net table.
Below generally speaking, may use some conventions in view of the circuit wafer on different part:
1. part’s majority power source pin may neglect.
2. the usual electric capacity is serves as the decoupling, may simple neglect, because will do this will affect soon by between the simulation other digital part’s interconnection relations.
3. the inductance may also neglect, when simulation replaces with the short circuit.
4. the resistance may use Verilog on to pull/under pulls or the simple line on demand must replace.
5. the crystal oscillator may use the clock module replace which in the Verilog storehouse provides.
May define certain peculiar circumstances in the restraint document, and as script input. May be the Verilog module compiles Wrappers to overcome the main line statement question. This kind of top layer Verilog net table may replace the top layer Verilog document which in the DUT function confirmation already uses, and uses in confirming in the environment.
FPGA prototype board net table simulation
Hence in the top layer Verilog document has contained on the prototype board part’s all parts which deletes besides the tool. The designer may the multiplying DUT function confirmation use have the simulation environment. This method’s merit lies, may the multiplying same test vector and the confirmation environment confirmation schematic diagram.
Any confirmation environment’s basic principle is the same, is DUT provides some form the test vector, then to tests the result and the expected value carries on the comparison. Has the way which according to the design complexity many kinds of achieves. Was very good through the following this very simple example understands. The example is one based on x86 processor’s SOC. For simplicity, we only considered that shown in Figure 1 in SOC the few important parts. DUT by the x86 processor, the main span (Host Bridge), the SDRAM controller and the PCI bridge is composed. In confirmation environment, to raise the simulation velocity, may regard as the x86 processor is BFM, simultaneously provides some kind of PCI from the model. Puts briefly, x86 BFM has some form to read/writes the order, can have the bus cycle, therefore designs may move.
The chart 3:Verilog module founds the wrapper matching unit’s pin
As shown in Figure 2, the main span and the SDRAM controller are mapped the FPGA1, PCI bridge maps when FPGA2. The top layer Verilog document which produces by the script contains all parts which as shown in Figure 2. Hence may use this top layer Verilog document conveniently in the confirmation environment, and attaches in the same verification test vector. What must pay attention is also needs to found the wrapper matching unit’s pin for each Verilog module. Regarding SDRAM and the PCI mortise, may use the same model which and in the RTL confirmation environment uses (i.e. the SDRAM model and PCI main/from model). The reference diagram 3, carry on FPGA1 as the case the explanation.
Because has only made the few revisions to the environment, if increases the very few Verilog document in the translation tabulation (the wrapper model), with file replace top document which founds newly, therefore may to the schematic diagram tabulation implementation confirmation. These matters may realize the automatic reduction through simple perl or the shell script, the entire duty will reduce to only assigns some special options, simultaneously obeys orders issues an order the movement simulation.
If has any wrong connection, or certain connections are forgotten, then the simulation result will have the corresponding prompt. This method may realize to with analog element’s connection part test, because this part of part some deleted from the net table, some are replaced by the equivalent behavioral model. However, some mistakes may pick out.
The silicon chip lives the forming network table the simulation
The above method may use for the simulation design similarly to use in testing the final silicon chip’s circuit wafer net table. This method is suitable for to these board confirmation, because in the normal condition makes many board its chip’s parallel test is may complete. In addition, disposes the FPGA pin through some way to be possible to eliminate based in the FPGA board mistake. Below continues by the preceding text example to explain how to apply the identical concepts the silicon chip to live in the forming.
As shown in Figure 1, silicon chip equivalent in DUT. Founds a Verilog net table according to the same flow, this net table regards as DUT is on a board chip and other auxiliary equipment. This is the top document which must use in the confirmation environment. Now we already had DUT complete Verilog to describe, therefore only needs Verilog wrapper which founds shown in Figure 4, lets on the pin output and circuit board the chip match.
In summary, this net table is may use the beforehand use the identical test vector to carry on the operation.
This article subtotal
This method underwent the test, at present correct use in schematic diagram confirmation. This method increased the new plan for the schematic diagram confirmation. The prototype/lives the forming the schematic diagram confirmation and the error detection may in extremely easy have the serious problem and affect the design cycle the early stage to carry on. Moreover, the confirmation does not need the extra expenses, what because this method based on was the field often says the `multiplying ‘ the principle, what in this case multiplying was tests the vector and the confirmation environment.
Chart 4:Verilog wrapper lets on the pin output and circuit board the chip match
Reference:
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Thomas & Moorby’s, The Verilog Hardware Description Language, Third Edition, Kluwer Academic Publishers.
Ellie Quigley, PERL by Example, Pentice Hall PTR.
John R. Levine et al, Lex & Yacc: O’Reilly & Associates, 2nd edition October 1992.
Brian W. Kernighan, Dennis M. Ritchie, The C Programming Language, Second Edition, Prentice Hall Of India Pvt Ltd.
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