Abstract: Introduced that one kind based on the cPCI main line’s point-to-point high speed data optical fiber transmission system, proposed completes the connection card design and the follow after higher transmission speed thought with the scene programmable large scale integration logic component substitution discrete component, and the actual design has realized this idea. Introduced emphatically system’s hardware architecture design and the software function realized, have given the main chip model which selected. The experiment proved that this system work was stable, has met the design target requirements.
Key words: cPCI main line, FPGA, data transmission, PCI9056
1. introduction
The high speed data transmission system design’s key is the host interface card design with realizes. The traditional procedure uses the discrete component, constitutes by certain modules. The majority designs are similar to following structure [1]: Connection major function module including electro-optic signal conversion connection (O/E and E/O), serial conciliatory serial module (TX and RX), data buffer F I F O, c PCI controller and programmable logic module (FPGA either CPLD) or DSP. In various modules O/E and E/O realize between the optical fiber channel serial light signal and the serial electrical signal’s interconversion. TX and RX realize the serial electrical signal and the parallel electrical signal’s interconversion function. F I F O mainly realizes between the optical fiber channel and cPCI the signal cushion. the cPCI controller realizes the FIFO output signal and 32 standard cPCI signal transformation. FPGA or CPLD are responsible for between various modules succession coordinated and the transmission control. Analyzes the above plan to be obvious, various modules function is completes by the separation chip. Like this interconnection between various chips’ will affect the transmission speed inevitably, also will cause the PCB board the layout wiring will become complex, will cause the transmission time delay to increase, will further cut the transmission speed. But along with FPGA (Field Programmable Gate Array) technical unceasing development, its capacity, function, reliability as well as speed of response in unceasing enhancement. Definitely may realize the computer and between the optical fiber channel’s data transmission and processing with piece of FPGA. In view of this, present paper’s design will use piece of FPGA to realize serial signal and parallel signal interconversion, data buffering as well as succession coordinated and transmission control and so on before the functions which with the discrete component realizes.
2. the system principle and realizes
This system by two PC machine, two connection cards and an optical fiber is composed. The system design key is based on the cPCI main line’s connection card. The connection card uses the standard the 3U board design, by the bus control unit chip, the programmable logical controller, the electro-optical transformation driver and so on is composed. Its structure diagram following chart shows.
Figure 1 system schematic diagram
This system design’s goal is applies in the radar data transmission, mainly solves the point-to-point data transmission problem. For high speed, reliable transmission radar signal, decided that uses the optical fiber to take the transmission medium, loses, the antijamming ability using the fiber optic transmission to be strong slightly fully, transmission speed higher merit. Its work flow is this: Transmitting end PC machine the data which is going to transmit through the cPCI connection sends in FPGA, FPGA to carry on after the data signal actuates and realizes the signal processing process which the data buffering, and the string transformation and so on must forms the serial signal, the serial electrical signal transforms the serial light signal after the electric light switch to send in the optical fiber to carry on the transmission. In the receiving end, transforms after the electro-optical switch the light signal the serial electrical signal to send in FPGA, FPGA to carry on to the data signal actuates and realizes the string and transforms the signal processing process which, the data buffering and so on must, then enters PC machine through the cPCI connection to carry on the memory to wait for the analysis processing. The design mainly divides into the hardware design and the software design two parts.
First, hardware design part
General, this design is mainly must complete the host interface realization. The host interface is realizes the high speed data transmission and a data storage key link. Mainly completes the high speed data stream the signal conversion, realizes the data on main engine’s memory, simultaneously reduces CPU to save the process the intervention. CompactPCI is called cPCI, is the international PICMG association one kind of bus interface standard which raised in 1994. Its appearance has solved the delicate matter which for many years telecommunication system engineer and the equipment manufacturer have faced: Inexpensive easy to use the VME crowded firm seal and large-scale equipment’s side good cooling performance as well as PC have the newest handling ability chip to unify in together, both guarantees 99.999% high reliabilities, and reduces the hardware and software’s development cost. Therefore the hope completes the data through the cPCI main line using the DMA way the transmission and the memory. By Figure 1 the knowledge, the connection major function module including the electric light (electro-optic) the signal conversion module, programmable becomes logic module FPGA and the cPCI bus interface module. In connection various modules, O/E and E/O realize the light signal and electrical signal’s interconversion. FPGA realizes the nearly all signal processing work, for instance realizes the data serial, the parallel transformation with to carry on the data transmission finally through the optical fiber; Realizes the FIFO function clear signal cushion, in the high speed data transmission the buffer is very important, it has been coordinated between the data transmitting end and receiving end’s data transmission speed, prevents, because the data stream speed’s fluctuation causes the transmission the defeat; Realizes between various modules succession coordinated and the transmission control and so on. the cPCI bus interface card realizes the FPGA output signal with 32 standard cPCI signal transformation, realizes the cPCI main line through the DMA way to main engine’s data storage. Main research and design key in cPCI bus interface module, programmable logic module FPGA and electro-optical transformation module.
(1) cPCI bus interface module
At present, the cPCI bus interface’s design and the PCI connection’s design is the same, generally uses two kind of plans, then programs the logical component and the special-purpose bus interface component. The programmable logical component is realizes the PCI bus interface controller according to the PCI agreement in FPGA or CPLD, but as a result of the PCI agreement’s complexity, causes the development difficulty to be big, the cycle is long, moreover very difficult to achieve the system to be stable in a short time, this method is quite suitable in the production in enormous quantities situation. Regarding the common exploiter, uses the ready-made PCI connection component mostly. This kind of specific interface component has the low cost and the versatility, can optimize the data transmission, provides the disposition space, has uses in the burst transmission function internal FIFO and so on, is plan which one kind time-saving reduces effort. This kind of special-purpose chip has many, like PLX Corporation’s PCI main line goal connection component PCI9052, PCI9054, PCI9056, AMCC Corporation’s S5933 and so on. Because the cPCI main line’s clock rate is 66MHz, the data width is 32, therefore in this design selects PLX Corporation’s specialized bus interface chip PCI9056 to take the bus interface controller, it conforms to the PCI2.2 standard, is 32, 66MHz PCI the bus master I/O accelerator, is suitable in general 32, the 66MHz local bus design, the local bus burst speed may reach 264MB/s, supports the DMA channel, the FIFO buffer is big, is a section of performance-to-price ratio quite high chip. Its local main line may be three kind of patterns: The M pattern, the C pattern and the J pattern, may choose using the pattern choice pin. This design selects the C pattern, namely 32 address/data bus non-multiplying.
(2) programmable logic module FPGA.
FPGA has selected altera Corporation Stratix GX series EP1SGX10CF672[2]. Stratix the GX component series is the Altera second generation based on the transceiver FPGA series, for needed to reach as high as the 3.125Gbps data rate the application to provide a low risk to realize the way. Stratix the GX kilomegabit transceiver function block is the embedded transceiver function block, it has four full-duplex channels, uses the clock data recovery (CDR), the transmission speed reaches as high as 3.125Gbps. Each channel has realizes the data recovery/transmission, serial/Xie Chuan, the decoding/code and the synchronous processing and so on different period allocated-use circuit. Has guaranteed the reliable data transmission with the programmable logical organization’s seamless connection, the biggest data volume of goods handled and the simplified succession analysis. Its compatible optical fiber channel, connection agreements and so on serial Rapid I/O, integrate the 8b/10b codec encoder-decoder. This design mainly used its 8b/10b to arrange the decoding module and the optical fiber channel protocol. Moreover, this model of chip interior includes PLL, and its internal FIFO buffer is quite big. Is precisely as a result of this series chip function, the capacity as well as the speed of response large scale promotion, causes a piece of chip to complete many separation chips the function to become possibly, then raises system’s data transfer rate.
(3) electro-optical transformation module
The electro-optical transformation driver has selected Infineon Corporation’s V23818-M305-L57. This model of chip data rate reaches as high as 2.215GBd, the compatible optical fiber channel protocol, has the good EMI performance. Because this chip difference output signal’s level is PECL or LVPECL, then the surface FPGA high speed serial transceiver’s difference received signal level is PCML, two kind of interface standard’s syntype voltage is different, must therefore use the AC coupled circuit to complete two kind of levels the transformations. Coupling capacity’s choice already cannot too greatly not be able to be too small. If is too big, will slow down the signal seriously the transmission speed, because and the charging and discharging time is excessively long, will become to the fast change signal’s response very bad; If is too small, rerouting’s impedance characteristic, will increase the weaken. Overall evaluation these two kind of requests, coupling capacity’s Rong Zhi is quite suitable in 0.01 µ F. The exterior DC biasing circuit may omit, because Stratix the GX component’s high speed transceiver input base pin built-in has the DC biasing circuit, therefore needs the syntype voltage in the component interior production.
Second, software design part
The connection card’s software design mainly includes two parts, one is the FPGA control procedure compilation, one is the board card driver compilation. Following this article mainly on receiving end FPGA control procedure compilation detailed elaboration. Just like front states, FPGA mainly completes succession coordinated and the transmission control, as well as the data stream string and transforms and the buffer. Overall system’s control uses limited state machine [3]. Its phase transition chart is as follows:
Figure 2 Accepting state transformation chart
Under state machine’s phase transition as well as each condition signal processing completely based on PCI9056 Local end to PCI end DMA transmission succession chart. Its succession chart following chart shows:
The transformation flow divides into 3 conditions: idle, prel, dma_read. idle is the idling condition, after on electricity replacement, first enters this condition, the main line does not have any operation, only examines the ADS# signal unceasingly, once examines this signal to be effective, enters the next condition. prel is a state of transition. May know according to the PCI9056 DMA transmission succession chart, after each time a new main line turning on effective (i.e. ADS# effective) the first data will continue two clock cycles (after that data will continue a clock cycle), the first clock cycle will not gather the data, but only will be causes from the equipment to prepare the signal (i.e. READY#) effectively, the second clock cycle will only then start to gather the first data. Therefore, this state of transition is mainly causes the READY# signal to be effective in the gathering data preceding cycle. the dma_read condition period execution from the local bus to cPCI main line’s DMA operation, in clock’s rise along the gathering data, until burst length’s in last data, the BLAST# signal is each time effective, the next clock cycle, the state machine returns to the idling condition, the start which the waiting next time transmits. Processing defers to [4][5] which to the data the data flows completes gradually. The first serial data which transforms after OE enters FPGA, serial receives and dispatches the channel by way of the FPGA interior to complete the decoding and the first step string high speed and transforms, by now became the 8bits parallel data by the 1bit serial data; Because next the cPCI local bus data line width is 32, therefore the second step string and transforms must complete the 8bits data to the 32bits data transformation. Its process is, comes the continual lock with 4 8bits D triggers to save the input the 8bits data, uses 32bits the D trigger to come simultaneously the lock again to save 4 8bits the data to form the 32bits wide data output; Finally to carry on the cushion to the data, completes the data rate the transformation, stores 132 bit wide asynchronous FIFO the data. This asynchronous FIFO writes the clock is withdraws from the serial data along with the road clock, reads the clock is with the bus control unit PCI9056 partial clock frequency the exterior 66M clock which provides by the board on.
3. summary
This article author’s innovation spot lay in with high performance FPGA substitutes for in the tradition to use the discrete component design high speed transmission system’s method, thus simplified the circuit design, reduced interconnection between primary device’s, not only has saved the board card area, moreover enormous enhancement transmission speed. This topic the project which undertakes based on the laboratory, mainly uses in the radar data the transmission. The design target request sampling points are 16384, above pulse rate (PRF)6K. It is not lower than 50MHz based on this target request parallel data sampling clock frequency characteristic, such transmission speed may reach as high as above theoretically 200MB/s. The experiment proved that this system’s software and hardware design is successful. Not only this point-to-point high speed optical fiber data transmission system is suitable for the radar data transmission, simultaneously in aspects and so on high speed data gathering, remote control also has the broad application prospect.
Reference:
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4. GE ZHOU, YIMO ZHANG, WEI LIU, “Optical Fiber Interconnection for the Scalable Parallel Computing System”, PROCEEDINGS OF THE IEEE, VOL.88, NO.6, JUNE 2000
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