FPGA (scene programmable gate array), because it has the use nimbly, to carry out the speed to be quick, but the development kit rich characteristic more and more appears in the scene circuit design. This article takes the connection chip with FPGA, provides the control signal and the timing signal, realizes DSP to the SDRAM data access.
1 SDRAM introduction
This article uses SDRAM is TMS626812A, Figure 1 is its function diagram. Its interior divides into two, each 1M byte, the data width is 8, therefore the memory aggregate capacity is the 2M byte.
All inputs and the output operation are in the clock CLK rise along the function under carries on, refurbishing clock alternately refurbishing interior two RAM. TMS626812A mainly has six control commands, they are: The strip stirs up the sharp/good address entrance, the row address entrance/to write the operation, the row address entrance/to read the operation, the strip invalid, automatic refurbishing, automatic refurbishing. SDRAM and in the TMS320C54x connection uses the order mainly has: MRS, DEAC, ACTV, WRT-P, READ-P and REFR. Here, the design goal is produces the control signal to satisfy these orders the succession request. May examine its data book about the TMS626812A concrete showing.
Between 2 SDRAM and TMS320C54x general connections
Figure 2 is DSP and the SDRAM general connection diagram, in the chart DSP I/F represents the TMS320C54x end connection unit, SDRAM CNTL represents the SDRAM end interface control unit. SDRAM is established the disposable read-write 128 bytes, but a DSP read-write byte, thus established two buffer B0, B1 to come the buffer and the relay data. B0, the B1 size is 128 bytes, moreover maps in DSP the identical address space.
Although B0, B1 correspond to the identical address space, but cannot carry on the legitimate visit to two buffers in the identical time. In fact, when B0 by the DSP visit, B1 by the SDRAM visit, otherwise also establishes. If DSP writes the data to B1, SDRAM reads the data from B0; But when the SDRAM data writes about in B0, DSP from B1 reads the data. At the same time both will read from the identical buffer or writes will stimulate the mistake. Above states the data shift way has two kind of advantage: First, has accelerated the TMS320C54x access speed; second, has solved between the two’s clock not synchronization problem.
In 3 FPGA hardware designs
TMS320C54x was the exterior memory’s expansion has provided the following signal: CLK, CS, AO~A15, D0~D15, RW, MATRB, ISTRB, IS, but SDRAM receives the following signal: CLK, CKE, CS, CQM, W, RAS, CAS, A0~A11. Because the both sides control signal is different, needs adds on the control logic between DSP and SDRAM, with the aim of coming from DSP the signal explained SDRAM can receive the signal, Figure 3 is the top layer hardware interface chart which designs with FPGA.
In chart mainly by three modules: DSP-IQ, DMA-BUF and SD-CMD. And DSP-IO is the DSP end connection, uses for to decode TMS320C54x the transmission SDRAM address and the order. DMA-BUF on behalf of buffer BO, B1. The SD_CMD module uses for each kind of signal which has the SDRAM visit to need.
The DSP_IO module includes IO_DMA, DSP_BUF and DSP_READ. IO_DMA produces the SDRAM command signal, namely Figure 3 DSP_RDY, DSP_SD_RW, DSP_SD_BANK_SW, DSP_SD_ADDR [20..0], DSP_SD_ADDR_RESET, DSP_SD_START. DSP_BUF produces visits B0, the B1 address, the data and the control signal, Figure 3 middle finger DSP_SD_BUFCLKI, DSP_SD_BUFCLKO, DSP_SD_BUFWE, DSP_SD_BUFADDR [6..0], DSP_SD_BUFIN [7..0]. The DSP-READ submodule uses for to control DSP the read-write direction.
DMA_BUF divides into B0, the B1 two buffers, uses for to carry on the data transfer, each buffer’s input/output signal includes: CLKI, CLKO, WE, ADDR[6-0], DATA_IN[7-0], DATA_OUT[7-0]. BANK_SW is a switching signal, uses in DSP and SDRAM visit to B0, B1 cut.
The SD_CMD module including refurbishing, reads, writes the function. When the DSP chip sends out SDRAM reads the order, 128 bytes data from SDRAM read and is saved to B0 or B1, when DSP sends out writes the order, 128 bytes data pass to B0 or B1 and finally is written in SDRAM.
4 software designs
TMS626812A SDRAM has two megabyte storage capacities. Therefore DSP visits SDRAM with two I/O addresses to the FPGA transmission the height address. In this article, these two I/O address to applies Figure 4 03h (DMA_ADDH) and 04h (DMA_ADDL). Moreover, but also some I/O address (Figure 4 05h) uses for to the FPGA transmission order to produce the SDRAM visit signal.
DSP writes when the data to SDRAM the sequence of operation is as follows:
(1) the data is written about first B0 or B1.
(2) the SDRAM visit address and DMA_ADDL transmits by way of DSP I/O address DMA_ADDH to FPGA.
(3) DSP issues an order to FPGA (the I/O address is DMA_CTL) produces the control signal, causes SDRAM reads the value from B0 or B1.
DSP reads data from SDRAM the sequence of operation to be as follows:
(1) the DSP transmission visits SDRAM the address.
(2) DSP transmits an order by way of FPGA, causes the data to read in FPGA from SDRAM.
(3) DSP reads the data from B0 or B1.
Figure 4 is in DSP and the data transfer related each kind of memory’s assignment situation.
When concrete design, should refer to the correlation data to carry on the supplement. When different DSP and different type SDRAM connection, will have the slight difference, after the circuit design finished, must carry on earnest and the various test.
