In CNC (computer numerical control) processes, the laser cutting, the automated roll arc welding system, to step-by-step/the servo motor control and other by in the motor control machinery assembly setting movement control system, the PID controller applies widely. Its design technique is mature, since long formed the model structure, the parameter installation has been convenient, the structure change was flexible, could satisfy the general control the request.
This kind of motion control system is accused the quantity often for simulation quantities and so on speed, angle, is accused between the quantity and the setting value magnitude of error after discretization processing, may the control algorithm which realizes by the digital PID controller operate, finally transforms again into the simulation quantity feedback for the controlled plant, this is in the PID control commonly used approaches the principle approximately.
Uses this kind of structural design the control system, its performance can only with the original stepless control system performance be close, but will not surpass, will approach the precision with the continual mathematical model size which and sampling period length related [1] will transform. In the high speed motion control’s situation, sampling period’s influence is specially bigger, when the sampling period is relatively long, approaches the degree to be only then good, but so on also set a higher request to the PID control algorithm’s operating speed and return route’s control time.
The programmable logical component FPGA logical gate number is 5000 ~ 2,000,000, belongs to the large-scale even ultra large-scale logical component, its operating frequency is highest may reach 250MHz. Therefore, regardless of from the programming scale or the working speed, definitely may use for to realize the high speed PID controller. This design uses Altera Corporation’s Cyclone series FPGA component EP1C3 to develop the platform as the hardware, the commonly used increase type digit PID control algorithm carries on optimized processing to the motion control, raised the operating speed and return route’s control time. 1 increase type digit PID control algorithm’s FPGA realizes
The classics PID governing equation is:
In the formula, KP is the proportion magnification factor; K1 is the integrating time constant; KD is the differentiating time constant. Digital PID control algorithm’s realization, must use digital approximation the method. When sampling period quite short-time, replaces the integral with the summation, replaces the derivative with the difference quotient, causes the PID algorithm discretization, after will describe continuously a time PID algorithm differential equation discretization, the difference, combination processing, may result in:
May see from (2) type, increase type digit PID algorithm, so long as stored up recent three erroneous sampling value e(k), e(k-1), e(k-2) to be enough. Realizes this increase type digit PID control algorithm structure drawing as shown in Figure 1.
Figure in 1 dashed line frame’s structure is three has the shifting function multiplier, may use the process strict test which and the optimized processing great functional module Altera Corporation provides LPM_MULT(M0~M2) realizes. LPM_MULT is one may have custom-made the bit wide the addition/multiplier, here, has custom-made erroneous input value e(k) the bit wide is 8bit, after another constant multiplicator q0, q1, q2 are the installation PID controller’s controlled variable, the bit wide are 6bit, the multiplier output result bit wide are 14bit. In QuartusII schematic diagram as shown in Figure 2.
The LPM_MULT great functional module may also have custom-made when the operation result output waited for that synchropulse (clock) the integer, this is the LPM_MULT assembly line output function. In Figure 2 assigns lpm_mult0, lpm_multl: the lpm_mult2 standby period is 1, 2, 3 synchropulse in turn, this kind of design has realized the shifting multiplication operation naturally; Meanwhile using multiplier’s assembly line function, raised the multiply operation speed. After optimization function simulation profile as shown in Figure 3.
By Figure 2, chart 3 obviously, jumps in Kth assembly line advancement clock signal clk on along, lpm_mult0 outputs under the current time product operation result steplout, lpm_multl to output K under one 1 time product result step2out, lpm_mult2 to output K-2 under the time product result step3out, the parallel addition arithmetic unit parallel_add value of exports is result=steplout step2out step3out.
2 general mold/numbers, number/mold switch’s design and simulation
For does not lose system’s versatility and the extendibility, refers to ADI Corporation 8bit, half twinkle A/D the switch AD7822 succession chart, designed general A/D switch block typical_adc to realize system’s mold/number transformation simulation function. the typical_adc part is an idealized A/D transformation chip, mainly by a 8 bit address counter and a depositing sine data’s ROM constitution, it simulates the sinusoidal signal the sampling, the quantification process, the sampling period only with system’s work clock related [2].
Is opposite transforms in the mold/number says, the number/mold transforms the control signal wants few somewhat, the succession request is simpler. Refers to TI Corporation 14 D/A transformation chip DAC8806 the function table, designed general D/A switch block typical_dac to realize system’s number/mold to transform the simulation function. For the formalized expression system’s D/A switching process, typical_dac was only △u(k) makes a parity check operation to the PID algorithm output, the VHDL language description has been as follows:
ARCHITECTURE behav OF typical_dac IS
When BEGIN- switching control signal wr is the low level outputs each different or the value, otherwise output high-impedance state
uout<=(datain(0) XOR datain(1)XOR datain(2)XOR datain(3)XOR datain(4)XOR datain(5)XORdatain(6) XOR datain(7)X0R datain(8)XOR datain(9):XOR datain(10)XOR datain(11)XOR datain(12)XOR datain (13)XOR `1 `) WHEN wr= `0 `ELSE `z `; END behav; ;
3 work control state machine’s design
The typical digital PID control system transforms, the PID control algorithm and D/A by A/D transforms three key link constitutions. In order to be coordinated between three links the work flows, the system work control portion is essential. The pure hardware number system’s sequential control has many kinds of plans to be possible to elect, like monolithic integrated circuit secondary control, embedded CPU soft nucleus control, pulse counting control and so on, but with difficulty gives dual attention to system’s high-speed controls and the nimble expansion. In the high speed operation and the control aspect, the limited state machine has the superiority which the above several control mode surmounts with difficulty.
From state machine’s signal output way the minute, has Moore and the Mealy two kind of state machines. Looked from the output succession that the former belongs to the synchronized output state machine, but the latter belongs to the asynchronous output state machine. The Mealy state machine’s output is the current condition and all input signal function, its output is after the input change occurs immediately, does not rely on clock’s synchronized [2].
The Moore state machine loses the origin is only the current condition function, this kind of state machine when the input changes must wait for that clock’s arrival, the clock causes the condition changes when only then to cause the output the change, therefore confidential waits for a clock cycle compared to Mealy, but can avoid the burr phenomenon effectively. This design uses state machine for the single advancement Moore state machine. Phase transition as shown in Figure 4.
4 systems realize with the function simulation
The entire PID controller’s system design uses the design method and the modular design concept from the top, namely obtains the VHDL system behavior by the PTD controller’s natural language description to describe first, then decomposes to the system into the erroneous A/D transformation part, the PID arithmetic unit, control increase D/A transforms as well as is coordinated three control state machines and so on four main modules.
Altera Corporation special-purpose EDA the software QuartusII support schematic diagram and the VHDL language mixed admission design way, selects the schematic diagram input design method besides the PID arithmetic unit, other three parts select the VHDL input design method. When system simulation, if the systematic most senior engineer will make the speed hypothesis will be 120MHz, then the sampling speed is 24MHz. Function simulation oscillogram as shown in Figure 5.
Through to increase type digit PID control algorithm’s optimized processing, obviously raised system’s working speed. The simulation result indicated that has the low slewing rate A/D converter technique to become raises the systems operation speed the bottleneck. The twinkle A/D component which uses on this design says, reduces the state machine to wait for A/D transformation conclusion signal EOC (see Figure 4) the time, namely raised the speed which A/D transformed is raises the system whole working speed the key.
In this design uses the increase type digit PID control algorithm’s design concept may apply the finite unit pulse to respond the (FIR) filter and the infinite long unit pulse response (ⅡR) in filter’s FPGA design, and may use the assembly line optimization techniques similarly to raise the working speed. At the same time, because PLD design and special-purpose ASIC design versatility, in PLD designs the design which in the platform completes to be possible very natural to transit to the special-purpose ASIC project work, further enhanced system’s reliability and the integration rate.
