Image gathering is the real-time imagery processing important step. At present, the image sensing component mainly has CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor). The CCD technology already was now mature, the CCD camera was still the high-end application first choice component. It outputs simulated video signal including image signal, line and field blanking wave, line and field synchronizing signal and so on seven kind of signals. The traditional video frequency gathering system by a/D switching circuit, the control logic circuit, data constitutions and so on buffer electric circuit, address generator, address decoding electric circuit, this kind of design has the electric circuit to be complex, the chip is many, the development cycle is long, cost higher shortcoming.
This article used the video frequency decoding chip and complex programmable logical component CPLD (Complex Programmable Logic Device) has designed a set of real-time image gathering system, has overcome the above shortcoming. And the video frequency decoding chip may from the video signal the automatic gain line, the field synchronizing signal, and completes A/D to transform, but has in the system programming (ISP) function CPLD may realize logical restructuring through the software, electric circuits and so on logical control, address generator integrates completely in a chip. The system has the volume to be small, the cost is low, the reliability is high, the promotion is easy, development cycle short and so on merits.
1 video frequency decoding chip SAA7114H performance characteristic [1]
SAA7114H is a high integration rate electric circuit, has the widespread application in the video frequency gathering domain. The video frequency decoding based on the line of fixed clock decoding principle, can PAL, SECAM and the NTSC service pattern signal transforms into and the ITU601 standard compatible standard video signal. SAA7114H can receive TV the CVBS signal or the VCR S-VIDEO signal, simultaneously (X port) can also receive the MEPG symbol stream or VIDEO through its expansion connection the PHONE symbol stream digital video signal. After SAA7114H decoding video signal, but can also act according to the actual application, chooses 8 or 16 bit width data output forms.
The SAA7114H primary mission is the capture and the reproduce by pantograph video image, provides the standard to the display control switch the YUV digital video class output format. The SAA7114H main feature is as follows:
(1) pair of each group CVBS either the Y/C input signal may select the programmable static gain or the automatic gain control.
(2) includes two 9 video frequency A/D converter, may receive the digital CVBS signal or the Y/C signal input in the expansion connection.
(3) digital phase-locked loop is suitable for each kind of standard and the non-standard video frequency supply oscillator synchronous processing and clock’s production.
(4) horizontal and vertical sync signal examination.
(5) produces in the piece conforms to the ITU601 standard line of fixed clock.
SAA7114H also provides a I2C connection, uses in connecting with the master control chip, thus may carry on the read-write operation to its internal register, controls SAA7114H the active status.
After the SAA7114H decoding’s video signal, must maintain the correct succession corresponding relationships, can restore the original video image unmistakably completely. SAA7114H output succession including good field synchronizing signal, good field blanking wave, line frequency field repetition rate, field identification signal and so on. Take the PAL system signal as the example, its line, field succession relations as shown in Figure 1.
And, the HREF signal is the line blanking signal, VGATE (may through carries on determination on behalf of the field blanking wave to register VSTO[8:0] and the VSTA[8:0] programming), HREF and the V123 signal binding energy judgment current for the wonderful field perhaps occasionally the field, FID is the field identification signal. Above various signals can carry on the output through the SAA7114H related base pin (for example RTSO, RTSI, XRH and the XRV base pin and so on).
2 complex programmable logical component XC95216 performance characteristic [2]
XC95216 is the Xilinx Corporation’s one complex programmable logical component, has the rich programmable I/O pin, to be programmable in the system, easy to operate nimble characteristic. Not only may realize the conventional logical component function, but may also realize the complex sequential logic function. Its major function characteristic is as follows: Reaches 166 user I/O pin, all pin’s foot is 10ns, fCNT may reach a 111MHz,216 great unit to the foot logic detention, has 4800 available gates.
3 real-time image gathering system composition and principle of work
This article designs the real-time image gathering system is one based on the DSP moving target tracking system’s image gathering part. DSP the digital image signal which provides to the image gathering part carries on related computation processing, the target discrimination, then the control related equipment, achieves the tracking object the goal. System request timeliness is strong, the volume is small.
In the design uses video frequency decoding chip SAA7114H the simulated video signal conversion which obtains the CCD camera for the digital signal. In this real-time imagery processing system, constant speed video frequency decoding chip SAA7114H and between the speed change DSP imagery processing needs to join the cushion circuit. The cushion circuit has 3 kind of structures generally: Double mouth RAM structure, FIFO structure, pingpong buffer structure. The first two kind of cushion structure’s storage capacity is relatively small, is not the especially qualify high speed imagery processing system. The pingpong buffer structure’s characteristic had decided may use relatively cheap high speed large capacity SRAM, the periphery logic component constitution the buffer storage which to need compared to pair of mouth RAM as well as the high speed FIFO more suitable video processing system. Uses CPLD to control two SRAM by the pingpong way work, realizes the data stream in system’s high speed transmission.
3.1 video frequency gathering work flow
Video frequency gathering hardware diagram as shown in Figure 2. After system reset, monolithic integrated circuit (MCU) through the I2C main line to the SAA7114H initialization. The monolithic integrated circuit uses Philips Corporation’s P89C61X2BN, has in the system programming function, the permission changes the SAA7114H initialization routine, and may burn writes about in monolithic integrated circuit FLASH, is quite convenient. After initializing successfully, SAA7114H starts to work, will input the simulated video signal conversion 720×576 YUV422 digital signal, then inputs CPLD. CPLD carries on the format conversion at the same time, outputs YUV4:1:1, the CIF form digital signal, on the other hand also takes the address generator, inputs SRAM together with the CIF formatted data. CPLD also produces the SRAM read-write control signal, uses two piece of SRAM, by the pingpong way work, each piece preserves an image. Figure 2 the middle finger with aims at DB[7:0] to the DA[7:0] solid arrow the dotted arrow to express that the CPLD D[7:0] port’s data transports in turn gives DA and the DB port. After preserving the good image, the CPLD interrupt mode informs DSP to make corresponding processing.
3.2 pingpong buffer control principle
“the pingpong operates” is applies frequently in the data flow control processing skill. Typical pingpong operating procedure as shown in Figure 3. The pingpong operates the processing flow is as follows: The input data stream passes “the data-in choice unit” (in this gathering system, CPLD internal logical organization completes this data access function), isochronism assigns the data stream to data buffer SRAM A and in SRAM B. In the first time, the data stream buffer which will input to SRAM A. In the second time, passes “the data-in choice unit” the cut, will input the data stream buffer to SRAM B, at the same time, the SRAM A data (first image data), passes “the output data choice unit” the choice, delivers “the data stream operation processing module” (DSP) to operate processing. In the third cushion cycle, passes “the data-in choice unit” the cut once more, will input the data stream buffer to SRAM A, at the same time, (second image data) passes the SRAM B data “the output data choice unit” the cut, delivers “the data stream operation processing module” operation processing. So the circulation, starts once again.
The pingpong operates the most major characteristic is passes “the data-in choice unit” and “the output data choice unit”, according to the metre, coordinates the cut mutually, will not stop after the cushion data stream delivers “the data stream operation processing module”, carries on the operation and processing. Operates the module the pingpong to treat as a whole, this module both sides’ input data stream and the output data stream are continuously, does not have any stop, therefore very suitable to carry on assembly line type processing, completes the data the seamless cushion and processing.
3.3 CPLD designs
3.3.1 data buffers
Data storage SRAM, must produce the address while sampling. Each SRAM address wire has two groups, a group gives by CPLD, a group gives by DSP. In order to solve uses in common time memory’s resources conflict question, must control between DSP and SRAM, CPLD and SRAM make-and-break [3]. CPLD through provides the main line disconnector the control signal, when CPLD to SRAM A operation CPLD to the SRAM B address wire, the data line, selects patches or strips of land as worth saving for seed the signal to set high-resistance, the establishment disconnector causes DSP and SRAM the B breakover, but separates with SRAM A, this time DSP may read SRAM B, vice versa. In fact, the SRAM data line also has two groups, its working and the address wire are the same. For reads in RAM for DSP by the abundant time the data, but must control each image stores different RAM, causes two piece of SRAM by the pingpong way work. In the design has selected ISSI Corporation’s IS61LV5128, the capacity is 512KB.
3.3.2 connections
The CPLD main periphery connection is as follows: (1) input section. Image data IPD[7:0], clock LCLK, field locking VREF, good synchronized HREF, repositions RES. (2) output unit. Image data IPO1[7:0] and IPO2[7:0], select patches or strips of land as worth saving for seed signal ce1, ce2, writes enables we1, we2, address add1[18:0], add2[18:0], main line disconnector switching signal f1, f2, DSP signal of stop dspint (here not to establish SRAM the OE signal, because CPLD only needs data to read in SRAM, does not need to read data from SRAM).
3.3.3 VHDL realizes
In the design uses VHDL to carry on logic to CPLD to realize. In the procedure “the pingpong” the control section code is as follows:
PROCESS (res, clk, idq)
BEGIN
IF (res= ‘ 0 ‘) THEN
tadd1<= ” 0000000000000000000 “;
tadd2<= ” 0000000000000000000 “;
add1<=tadd1;
add2<=tadd2;
count<= ” 00 “;
ELSIF (clk ‘ EVENT AND clk= ‘ 1 ‘) THEN
IF (idq= ‘ 1 ‘) THEN
IF (oddoreven= ‘ 1 ‘) THEN
tadd1<=tadd1 ‘ 1 ‘;
add1<=tadd1;
ELSIF (oddoreven= ‘ 0 ‘) THEN
tadd2<=tadd2 ‘ 1 ‘;
add2<=tadd2;
END IF;
END IF;
END IF;
END PROCESS;
This article has designed a set based on video frequency decoding chip SAA7114H and the CPLD real-time image gathering system, its hardware architecture is simple, the system is stable, satisfies completely based on the DSP moving target tracking system’s need, has the very strong usability, modifies slightly then uses in other situations, like supervisory system and so on.
Reference
[1] SAA7114H DATA SHEET,2000.
[2] XC95216 In-System Programmable CPLD DATA SHEET,2001.
[3] chapter of brave .CPLD and realizes in the video frequency gathering application. Electronic technology, 2004,(12).
