Along with digital technique’s progress, high speed, the ultra large scale integrated circuit widely uses, the 3G mobile termination baseband signal processing system toward nimble, integrated, modular, the universalized direction is developing highly. The baseband signal processor is the product which the digital technique and the communication unify, it can process the digital baseband signal nimbly, the modulation wireless signal in order to realize with the communication network system front end the base depot wireless communication. The article has designed one kind based on advanced microprocessor (ARM), digital signal processing (DSP) and scene programmable gate array (FPGA) the architecture 3G mobile termination baseband signal processor. This kind of architecture’s merit lies, when provides can meet the customer need the advanced processor, the overall system easy to integrate, moreover may increase the function conveniently through the software method, but does not need to have custom-made the non-erasable storage (ROM) code the new chip. Simultaneously the system use software realizes the union examination and the signal decoding function, with ease realizes through the software update to system’s any promotion, does not need the hardware to revise.
1 design mentality
Along with the real-time digital signal processing technology’s development, ARM, DSP and the FPGA architecture becomes the fundamental mode which the 3G mobile termination realizes. This article design carries on the modelling, the operation through ARM to the goal and the environment, the production network protocol simulation database, carries on the data dispatch, the operation and processing using DSP, finally forms control words and so on amplitude modulation which, phase modulation, frequency modulation needs, produces the radio frequency simulated signal through the FPGA control transceiver chip. Using digital chip between versatility, ARM and DSP correspondence, not can only the real-time processing receive the data which and transmit, but may also adapt the different motion network specific request, simultaneously facilitates loads the new procedure. The FPGA digit frequency synthesis technology take it in aspect and so on frequency agility speed, phase continuity, relative bandwidth, high resolution as well as integration outstanding performance, as the 3G mobile termination radio-frequency signal simulation realizes the way to provide the choice.
2 hardware realize
This system main part is the ARM master control module, the DSP real-time data processing module and the FPGA signal production module. The ARM master control module realizes the physical level and the agreement stack’s correspondence, receives the high-level instruction, carries out the corresponding task. If the agreement stack needed in certain sub-frames some either several upward time slot transmission data to the core network, in certain sub-frames some or several downward time slot receive core network’s data, by now deposits all instructions and the data in synchronized dynamic random-access memory (SDRAM), then informed DSP to carry out. After the DSP real-time data processing module obtains the data and the order, first processes the transmission data, carries on the channel coding modulation, CRC to the data to adhere to stick cohere, to interweave, the wide frequency modulation and so on, then the processing receive data, like the channel estimated that disturbs, the CRC verification, the channel decoding, the despread, only especially compared to the decoding and so on. FPGA is the signal production module, manages 26 M clocks, carries on the frequency division the duty, control simulation baseband (ABB) automatic transmission power control (APC), automatic reception gain control (AGC), automatic frequency control (AFC) and so on, simultaneously also real-time control radio frequency (RF) work. When in after DSP some algorithms are stable, may use FPGA to realize these algorithms, reduces DSP the processing burden. Its hardware circuit as shown in Figure 1.
2.1 connections
ARM and the DSP data exchange is realizes through pair of mouth stochastic memory (RAM), namely Figure 1 SDRAM, plays ascending-descending buffers and the exchange and so on control command, parameter and data role. Here receives and dispatches the pair of mouth RAM data line the figure size is 16 bit, the SDRAM memory size is 128 M. The hardware interrupt holding wire 8(INT8) produces mutually with hardware interrupt holding wire 9(INT9) every 5 ms one time, was equal to that the TD-SCDMA idle talk signal the sub-frame interrupts, simultaneously may also as ARM and the DSP control command, the response realizes between ARM and the DSP correspondence.
The FPGA main connection has the data_out[15:0] connection, with d/a converter (A/D) connection and with the RF connection.
the data_out[15:0] connection uses for to output the FPGA operation the result, hangs with the DSP data bus meets in the same place, establishes a three states of matter gate in the FPGA interior, the enabling signal is FPGA selects patches or strips of land as worth saving for seed signal CE. When CE does not select, the three states of matter gate output is the high-resistance condition, will not affect DSP the data bus. In each sampling point gap’s time, FPGA operates the correlative value the real part and the imaginary component, distinguishes the lock them to have 4 16 bit in the latches, and signal will set at the high level with DSP the connected data_ready, indicated that the data already prepared. DSP examines data_ready is Gao Houhui carries on reads the operation, produces with address bus’s high several selects patches or strips of land as worth saving for seed the signal to select FPGA, through address bus’s low two A0, A1 chooses 4 latches, reads the real part and the imaginary component two 32 figures in turn high 16 and low 16. The FPGA interior will read the operation counting to DSP, confirmed after the data will be divided 4 read-out, will set at data_ready lowly, finished after the next operation raised again. The FPGA frequency, the phase and the scope control word’s establishment and control signal’s production completes by TMS320C5510, FPGA may regard as is the asynchronous storage device and TMS320C5510 external memory connection (EMIF) is connected, EMIF uses 32 bit main lines.
With d/a converter (A/D) connection’s A/D end connection ABB, another end connection FPGA, the data which and the motion network receive data the transmission must transmit. With in a/D connection part, has 3 input end RIF, PS and CLK. RIF uses for the sampling point value which serial input A/D transforms; PS is the frame synchronizing signal, it in inputs uses for after FPGA to actuate the FPGA internal overall control module; Clock is shifts the clock, it controls between A/D and FPGA data serial transmission shifting.
Is mainly uses for with the RF connection to control transmits and receives the RF chip work.
2.2 master control modules
The master control module is responsible to control and to be coordinated each kind of work, ARM uses the open style multimedia application platform (OMAP) microprocessor which TI Corporation produces, may achieve 66 MHz through the integrated phase-locked loop frequency multiplication system basic frequency, the biggest exterior storage space may reach 256 MB, on the piece the fruitful in resources, the periphery control stubborn and unyielding person price scaled height of burst. Controls the DSP module receive network transmission by it the order and the parameter, realizes the wireless free agreement correspondence.
2.3 real-time data processing module
Real-time data processing module [1] realizes the transmission order, the transmission parameter and the data through the sharing memory and ARM, according to the hypothesis mobile termination active status, like Cell Search, stochastic turning on process (RA), dedicated control channel (DCCH), and the goal, the environment real-time dynamic calculates FPGA the control word. Simultaneously also gives ARM through sharing memory reporting from the network receive’s data and the intelligence transmission; Provides through the latch to the processing board controls the weaken control signal to realize the sleep, achieves the province electricity. DSP uses in TI Corporation C5000 series TMS320C5510, the system clock reaches 600 MHz, the data processing speed may achieve 4 800 MIPS. Provides 32/16 bit main engine mouth, has two independent exterior memory interfaces, EMIF supports 64 bit main line width.
2.4 FPGA module design
This article design uses the Stratix series chip, in inlays reaches 10 Mbit 3 kind of RAM blocks: 512 bit capacity small RAM, 4 KB capacity standard RAM, 512 KB large capacity RAM. The FPGA module has the True_LVDS electric circuit, supports low voltage difference signal (LVDS), low voltage emitter-coupled logic (LVPECL), accurate electric current pattern logic (PCML) and ultra mode of transmission (HyperTranport) the difference I/O electricity standard, and has the high-speed service connection. This design has provided the complete clock management plan, has the hierarchical structure and reaches 12 phase-locked loop (PLL). The Stratix series use’s development software is the new generation who Altera Corporation provides develops software Quartus II.
This series chip’s biggest characteristic is in inlays the hardware multiplier and while adds the structure the programmable DSP module, is suitable in realizes the high speed signal processing. This kind of DSP module is the high performance inserting arithmetic unit, it may dispose for the hardware multiplier, adds and subtracts the Buddhist musical istrument, the accumulator and the assembly line register. The Stratix series has reaches 28 DSP modules much, may dispose is 224 inserting multipliers, may provide nimble, highly effective and the valuable plan for the big data volume of goods handled application. These DSP module may realize many kinds of model DSP functions, like has the correlation instrument, to limit the impact on respond the (FIR) filter, the fast Fournier transformation (FFT) function and the encryption/decipher function and so on, the correlation instrument algorithm design is the foundation which and the basic building block each other algorithms realize.
The mobile termination system receives after front end the radio-frequency signal passes through pretreats, delivers a/D sampling, then through serial mode output sampling point value to FPGA[2]. Each sampling point value is with 10 bit binary system complement representations, must/and the switch transforms through a string for the width be 10 bit parallel signals first. First what the sampling point value must carry on is the Hill baud transformation, the Hill baud transformation has many kinds of realizes the method, here uses 129 steps the filter to realize, filter’s tap coefficient by MATLAB the function Remez production, obtains with its orthogonal another group signal; Then by these two groups signals separately as the real part and the imaginary component, carries on the related operation with the local sequence, gives DSP the correlative value real part and the imaginary component to make the following processing. Thus, DSP only then may through ask the mold first to the correlative value, then information and so on peak value gap which, peak-to-peak value and number appears to the mold value carry on the judgment and further process, determined whether to catch the signal. Correlation instrument algorithm FPGA design’s internal structure diagram as shown in Figure 2.
2.5 PFGA and RF connections, main line and sequential control design
FPGA and the RF connection, the main line and sequential control design as shown in Figure 3.
In order to increase the channel capacity, the improvement band width efficiency, TD-SCDMA through the use up link (reverse link) synchronized, the software radio and smart antenna’s technology unifies time division duplex (TDD) and CDMA. TD-SCDMA requests handset’s radiofrequency component to have the fast switching time, the high dynamirange as well as the transmitter and the receiver part high linearity. MAX2410 is a complete orthogonal launcher, it by an orthogonal modulator, variable gain IF and the RF amplifier is composed. MAX2309 is one kind for based on the CDMA monofrequent single model honeycomb telephone system design IF receiver, its input frequency range achieves 70 MHz~300 MHz after the optimization, in 35 dBm gain issuing - 33 dBm, issues 1.7 dBm in the - 35 dBm gains. FPGA controls RF mainly through 4 RF control register: A word register, B word register, C word register and D word register.
3 softwares realize
Mobile termination software including application layer software, communication protocol software and physical level software 3 parts.
Application layer software LAY 4-7: Contains man-machine contact surface (MMI) and the system application layer agreement (S/W) part, MMI is the mobile termination user connection, the S/W similar mobile termination operating system.
Communication protocol software LAY 2-3: This part of softwares are big, is mainly the communication protocol, the main guarantee wireless communication system may in each kind of condition smooth intercommunication.
Physical level software LAY 1: Is responsible to be coordinated DSP, other hardware and the software. The physical level software’s design will be able to realize the energy conservation characteristic, the multi-resources, multi-time slot processing, the data packet and to other network system’s monitor. In the design physics level software time must to the neighboring plot monitor, specially when between the neighboring plot each other did not have synchronized time.
Mobile termination software each module mainly realizes with hardware’s corresponding relationships is as follows:
Application layer software LAY 4-7 and the communication protocol software LAY 2-3 softwares realize are mainly realize in ARM, if LAY 4-7 need some specially high request time the application, may increase the corresponding hardware module again, but does not affect the original construction, if increases requests multimedia processing and the broadcast high; Physical level software LAY 1 mainly realizes in DSP and FPGA.
When the software programs ARM and DSP may use the C language to realize, the use debugging aids are the CCS software, when in after DSP has some algorithms are mature, the mobile communication when is quite high to this timely request, should use the assembly language to realize, may use the VHDL language in FPGA to realize. Is first as far as possible defines each functional module in the programming the duty, then defines each functional module the connection parameter and so on, in may not use the global variable time does not use as far as possible.
Another main challenge is realizes the union examination algorithm in the TD-SCDMA terminal, specially about algorithm time optimization. Between DSP and in the FPGA task allocation must have a reasonable coordinated division of labor, like this can the display these two processor’s function maximum limit. In the actual software programming, the algorithmic routine computation load is big, the code time delay is excessively long, therefore
Needs to carry on the optimization under the quality of certified level premise to the algorithm. In satisfies under the accuracy requirement, further simplifies the algorithm, the coarsening hunting zone reduces the computation load; Regarding the higher order language procedure code, with methods and so on mix assembly, elimination nesting loop carries on the code optimization, raises the code efficiency.
4 concluding remark
This experimental study is completes under the Nanchang University natural sciences fund Z03333 subsidization. This system very good has realized the 3G mobile termination processing function, but the actual environment is more complex than the simulation environment, needs to give the solution, then confirms again. At present this plan has realized 384 kb/s work, uses 3 time slots (each time slot 128 kb/s); Realized has turned on the (HSDPA) technology based on the high speed downward grouping to raise the data rate, it was similar the speed which provided in WCDMA and the CDMA2000 standard. The development 3G chip set can satisfy the consumer regarding the improvement performance and the function request, simultaneously maintained same or the lower price.
5 references
[1] Shanghai sensitive .DSP principle and in mobile communication application [M]. Beijing: People’s posts and telecommunications publishing house, 2002.
[2] Wakerly j f. The digit principle of design with practices the [M]. Beijing: Mechanical industry publishing house, 2004.
