Abstract: In the modern circuit design, a system has often contained many clocks, how to transmit the data in the asynchronous clock between to become a very important question, but uses asynchronous FIFO to be possible to solve this problem effectively. Asynchronous FIFO was one kind obtains the widespread application component in the electronic system, in the article introduced one kind based on the FPGA asynchronous FIFO design method. Uses this method to be possible to design high speed, high reliable asynchronous FIFO.
Key word: FIFO; FPGA
0 introductions
Between the different module’s data interface different clock system’s each module’s data interface is particularly a system design key realizes the connection in the scene programmable logic chip’s design process with the asynchronous FIFO module, connection both sides carries on under own clock’s synchronization works between them not to need to shake hand mutually only needs to carry on with the connection FIFO module alternately then namely to the connection FIFO module in the write data or from the FIFO module the readout. Realizes between the FPGA interior different clock system’s data interface with this kind of cushion FIFO module to cause the FIFO connection which the design becomes very simple and easy to use is the IP nucleus which XILINX Corporation provides. After the full test and the optimization, the FPGA interior resources which the systems operation takes stably are also few.
1 FIFO type
FIFO advanced left the formation is first one kind obtains the widespread application component in the electronic system usually to use in the data the buffer and uses in holding the asynchronous signal the frequency or phase difference FIFO realizes usually is use pair of mouth RAM and the read-write address produces Figure which the module realized 1 to demonstrate the FIFO internal structure.
Figure 1 FIFO interior structure drawing
FIFO function diagram as shown in Figure 2
Figure 2 FIFO function diagram
Writes the operation as well as the reset function different FIFO memory according to read-write operation’s synchronized/asynchronous symbol plan’s synchronized/asynchronous first may divide into 4 broad headings:
(1) asynchronous FIFO. Usually only then two control signals read enable (RE) with to write enable (WE) the marker signal to have entire symbolized spatially (EF) all completely symbolized (FF) may elect half-full to symbolize (HF) nearly all completely symbolized (AF) nearly entire symbolizes (AE) these symbols spatially not with any clock or the event synchronization, but reflection read-write indicator’s immediate comparison.
(2) selection type FIFO. Selects the FIFO usual use read-write with the asynchronous FIFO memory to select UNCK and the LDCK signal as well as the output similarly enables OE signal this kind of FIFO usually to provide half-full symbolized that (HF) may elect to symbolize nearly completely (AF) is nearly spatial symbolized (AE) entire symbolized spatially (EF) and all completely symbolizes (FF) these symbols, although reflection read-write indicator but not with any clock or event synchronization.
(3) standard synchronized FIFO. Synchronized FIFO needs to move freely reading and writes clock RCLK and the WCLK read-write operation is including reads with these clock synchronization control signal enables signal FEN to write enables signal WEN and the output enables the signal OE symbol plan to use entire symbolized spatially the entire full symbol and in the half-full symbol succession is not FWFT, therefore reads in FIFO the first character to pause first in one in the memory cell.
(4)FWFT synchronized FIFO. What FWFT First Word Fall Through FIFO and standard FIFO are similar it to need to move read the clock and write clock RCLK and the WCLK read-write operation including read with these clock synchronization control signal enable REN to write enable WEN as well as the output enable the signal OE internal structure are freely the first character directly through First Word Fall Through is reads in FIFO the first data unit to enter the output buffer directly, but is not stops in the storage location its symbol plan is the FWFT structure direct result also and standard synchronized FIFO is different. FWFT the FIFO memory use output prepares OR and the input prepares the IR symbol, but does not use the entire spatial symbol and the entire full symbol. FWFT FIFO also uses the midair to symbolize, may also choose the nearly entire spatial symbol and the entire full symbol.
2 FPGA internal soft FIFO design
In FPGA has several large capacity RAM, this article by XILINX Corporation Spartan-ⅡE series chip to design the chip. In Spartan-ⅡIn E series chip contains two row Block RAM, and places along the vertical nearby. As shown in Figure 3
Figure 3 pair of mouth RAM
Different Spartan-ⅡE series chip contains Block the RAM integer and figure as shown in Table 1:
Table 1. Spartan-ⅡE BRAM
|
Spartan-ⅡE series |
Integer |
Figure |
|
XC2S50E |
8 |
32/K position |
|
XC2S100E |
10 |
40/K position |
|
XC2S150E |
12 |
48/K position |
|
XC2S200E |
14 |
56/K position |
|
XC2S300E |
16 |
64/K position |
|
XC2S400E |
40 |
160/K position |
|
XC2S600E |
72 |
288/K position |
In FPGA soft FIFO by three parts of constitutions: Writes the address to have the module, pair of mouth RAM and reads the address to have the module. As shown in Figure 4
Figure 4. soft FIFO structure drawing
May see by Figure 4, writes the address to have the module basis to write the clock and to write the desired signal to have the increasing to write the address, reads the address to have the module basis to read the clock and to read the desired signal to have the increasing to read the address. The FIFO operation is as follows: In writes clock wr_clk rising along, when wren is effective, reads in pair of mouth RAM wr_data to write the address correspondence in the position; Will read the address correspondence in the pair of mouth RAM data output to read on throughout the data bus. This has realized the function which advanced leaves first. Writes the address to have the module also to act according to reads the address and writes the address relations to have the FIFO full symbol. When wren is effective, when writes address 2= reads the address, full is 1; When wren is invalid, when writes address 1= reads the address, full is 1. Reads the address to have the module also to act according to reads the address and writes the address the difference to have the FIFO spatial symbol. When rden is effective, when writes address - 1= reads the address, empty is 1; When rden is invalid, when writes the address = reads the address, empty is 1. Produces the symbol signal according to the above way is to a clock cycle produce the corresponding symbol signal ahead of time.
3 FPGA internal soft FIFO simulation
Scene programmable gate array FPGA is develops in the special-purpose ASIC foundation, it has overcome the special-purpose ASIC insufficiently nimble shortcoming. With other small scale integration electric circuit compares, it has the very strong flexibility, namely its interior’s concrete logical function may according to need to dispose, was very convenient to electric circuit’s revision and the maintenance present FPGA the capacity already to bridge over 1,000,000 levels to enable FPGA to become one of solution system-level design important selection schemes. Now FPGA already became many kinds of data acquisition system application the powerful solution. Day by day as a result of the programmable plan’s flexibility, the data acquisition system design may adapt the standard agreement which and the performance demand changes, FPGA has the integrated superiority and the lower system cost.
Really high speed integrated circuit hardware description language VHDL widely uses in describing number system’s structure, the behavior, the function and the connection. Its language form and the description style and the syntax are similar to the common computer higher order language.
This article uses XILINX Corporation Spartan-ⅡE series FPGA component scene programmed with VHDL has realized the soft FIFO design. In the Quartus II 4.0 environment the simulation, obtained the very good effect. The subprograms and the simulation result distinction like below procedure and shown in Figure 5.
Part VHDL procedure
…
FIFO1TO2:FIFO32TO32 PORT MAP
(wrclk=>FIFO1TO2WE,
rdreq=>FIFO1TO2RREQ,
rdclk=>FIFO1TO2RE,
wrreq=>FIFO1TO2WREQ,
data=>FIFO1TO2DATAIN,
rdempty=>FIFO1TO2EMPTY,
wrfull=>FIFO1TO2FULL,
q=>FIFO1TO2DATAOUT);
…
——————————PROCESS_FIFO_DSP1_TO_DSP2FIFO1TO2WRITE:PROCESS(FIFO1TO2WE)
BEGIN
IF (FIFO1TO2WREQ=’1′ AND FIFO1TO3FULL=’0′)
THEN
FIFO1TO2DATAIN<=DSP1DATA;
END IF;
END PROCESS FIFO1TO2WRITE;
FIFO1TO2READ:PROCESS(FIFO1TO2RE)
BEGIN
IF (FIFO1TO2RREQ=’1′ AND FIFO1TO2EMPTY=’0′)
THEN
DSP2DATA<=FIFO1TO2DATAOUT;
ELSE
DSP2DATA<= ” ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ “;
END IF;
END PROCESS FIFO1TO2READ;
Figure 5 part of against real results
4 conclusions
In the article in view of the asynchronous FIFO design’s in difficulty and the main point, proposed the concrete solution, and has given electric circuit’s design with the VHDL language, uses XILINX Spartan-ⅡE series FPGA realizes, and is applied in many kinds of electric circuits, has made the good progress in the practical application.
Reference:
[1] Xu Qingyuan, Zhang Tianxu, Zhong Sheng. Based on USB main line’s high speed video frequency gathering system design [J]. Micro computer information .2006,10-1:247-249.
[2] Yu Songhuang, Zhou Yuanhua the digital image processes the [M] Beijing: Electronics industry publishing house, 1987
[3] Martti Juhola.Comparison of Algorithms for Standand Median Filtering IEEE-TRANS ASSP-39 1991
the [4] forest is sensitive, Fang Yingli the VHDL number system design and the top level are comprehensive “M”. Beijing: Electronics industry publishing house, 2002
