The video frequency supervisory system in the train station, the airport, the bank, the recreation area, the market family’s security aspect is even one kind of key equipment. Along with security risk’s day-by-day enlargement, to has sent the event in each kind of application situation to carry on the video frequency monitoring and the record demand gradually is rising, this request video frequency supervisory system’s new structure must have the extendibility, in order to the diverse video frequency monitoring demand provide the high performance-to-price ratio day by day the solution.
In the video frequency supervisory system structure faces in the numerous challenges, the going on the market time pressure, CODEC new standard’s releasing and the demand scope expand (including high-level object detection, motion detection, target tracking and target tracking function) are also only a small part unceasingly. Must deal with these challenges, the video frequency supervisory system realizes must be able to act according to the different performance requirement to make the corresponding adjustment.
The Xilinx FPGA product is each kind of video frequency supervisory system ideal solution, no matter it is the low end system or the high-end system, is the independent system or the PC expansion card system.
Video frequency monitoring and DVR system
The high-level digital video compress technique is obtaining the fast popularization in video frequency supervisory system’s digital videocorder (DVR). Transfers along with the majority DVR manufacturers from MPEG4 uses H.264 high clear (HD) CODEC, to raises the resolution and the compression ratio request also becomes more anxious. Special-purpose standard product (ASSP) quite suitable quantity big application, but lacks the flexibility, moreover the development time is excessively long, the cost is also high. The majority high-level digital media processor company realizes H.264 the HD decoding quite to be difficult, much less H.264 the HD code is also much more complex than the decoding. Therefore, must satisfy H.264 HD the performance requirement, the preferred plan is uses FPGA to add together exterior DSP or the digital media processor together.
Uses the low cost Xilinx the FPGA product also to be able to further provide the motion detection, the video frequency quantification, the colour range to transform (color-space conversion), functions and so on hard disk connection, DDR2 memory interface, as well as data stream gathers two 27MHz ITU-R the BT656 through the multiplying is a group 54MHz data stream, simultaneously is the DSP processor provides the video frequency acceleration. After two ITU-R the BT656 data stream multiplying is one, the system only needs the single channel’s video frequency port to be able to transmit the entire double channel’s video data independently. This kind realizes the way when the connection has ITU-R the BT656 video input port’s digital media processor is practical. Shown in Figure 1 is the above recommendation system’s structure diagram.
Figure 1: Video frequency supervisory system which builds using FPGA and the digital media processor.
Speaking of uses only then single ITU-R BT656 video input port’s TI Da Vinci processor’s DVR design, more highly effective realizes the plan is before the data stream sends in the Da Vinci processor, two above ITU-R BT656 data stream multiplying for the single VLYNQ data stream. This kind of plan reduced has used in the video frequency data stream transmission the I/O base pin, thus reduced component’s seal, reduced the system cost. Shown in Figure 2 for this design diagram.
Figure 2: Video frequency supervisory system which builds using FPGA and the Da Vinci processor.
PC expansion card form DVR system
The PCI main line has succeeded on PC machine has applied 10 remaining years of life. But today’s PC the expansion card DVR system requests the band width has far exceeded the limit which the PCI main line can provide.
Compression video frequency (in after blank frame) the data rate approximately is 165 Mbps. Therefore, when the PCI total band width is 1 Gbps, on a PCI main line are most may simultaneously connect 6 transmissions not to reduce the video frequency the capture or playbacks the equipment. In order to reduce the main line band width occupancy, may use together MPEG4 or the CODEC chip set in the expansion card, but like this will enhance the cost, moreover may choose the component also to limit to the existing MPEG4 chip set.
PCI Express the (PCIe) technology had the very big enhancement in the current capacity. PCI Express may subdivide for many channels, each channel is leaving and enters contains a pair of difference to be right, to supports 2 Gbps every time to the difference the data current capacities. On a motherboard’s each PCIe slot has own channel, these channels not with other slot sharing. Each slot may dispose is 16 channels (i.e. x16), 8 channel (x8), 4 channels (x4) or 1 channel (x1). Therefore, each block uses the data current capacity which the PCIe main line’s expansion card may provide from 2 Gbps (disposition is when the x1 channel) to 32 Gbps (disposition is when the x16 channel). PCIe supports the high data current capacity lets us no longer only limit in each card connects 6 channels not to reduce the video frequency.
Uses design which shown in Figure 1, we can use PC machine to replace the digital media processor, and circulates the video frequency the PCIe main line to send in PC machine, thus with ease realizes set of PC fast the expansion card DVR system. The video frequency modulus switch produces 4 independent digital ITU-R the BT656 class, then sends in it a low cost the Spartan-3 component to carry on the pretreatment. This FPGA video data’s in blank and the synchronized elimination, and makes into it suits PCIe the data packet, then sends in it Xilinx the PCIe essence. Then from the software receive, the demonstration and the processing input’s video frequency, or saves it to the floppy disk. Figure 3 is this kind of PC expansion card video frequency supervisory system.
Chart 3:PC expansion card video frequency supervisory system.
Xilinx video frequency and imagery processing algorithm
Xilinx FPGA is the very ideal real-time digital video, the imagery processing and the filter platform, its function from the heterogeneity video frequency switch, the two dimensional FIR filter, the screen demonstrated that to covers (overlay) and Alpha the mix and so on simple effect even form and the colour range transformation and so on. Table 1 has listed some commonly used video frequency IP module group’s application guide.
Table 1: Video frequency IP module group application guide.
Xilinx FPGA unequalled DSP handling ability means that it may support the very high resolution (even is the 1080p picture quality), simultaneously reduces the large-scale DSP array the size. In addition, Xilinx FPGA may duplicate the hardware which programs, therefore very easily to carries on the experiment based on hardware’s high performance new video frequency and the image algorithm, thus direct achievement final product distinctive quality.
Practical IP resources
In order to speed up in the video frequency supervisory system the video frequency and the imagery processing algorithm design, the simulation, realizes with the confirmation advancement, Xilinx has also provided the rich video frequency IP module group, already includes designs the foundation simple algorithm which DVR needs, also contains the high-level algorithm.
Moreover, Xilinx and the partner has also provided a series of compressed encoding, the decoding and arranges the decoding plan, from for needs to realize on-hand merchandise essence which fast the design customer provides, to through cuts the bit rate for the hope to provide the higher picture quality, and realizes the modulation reference design which and the hardware platform by the product variation’s customer provides.
Uses Xilinx FPGA to complete certain arranges in the decoding module the extremely high strength processing duty to mean, not only the product may support the multichannel high clear code, save the precious system processor cycle, moreover may or eliminates through the reduction to the DSP processor array request achieves cost cutting truly, and relaxed more characteristics and the function (from connection characteristic to more formidable video processing function) will integrate the system. Most importantly, what FPGA provides is one kind may expand the plan, therefore may support the different system structure, the extra channel in the identical system or new arranges the decoding plan.
And realizes the new peripheral device through the enhancement system logic, Xilinx FPGA can also further reduce the DVR system’s cost. At the same time, Xilinx and the partner has also provided the following system connection for the fast development video frequency supervisory system: High-quality memory interface, PCI Express connection, TI VLYNQ and EMIF connection, hard disk connection, as well as ITU-R BT656 connection.
The tool which provides using Xilinx simplifies the design
Xilinx provides System Generator for the DSP permission uses Xilinx under Simulink the video frequency IP module group build and the debugging high performance DVR system. Uses System Generator to develop and to realize the video processing algorithm to be possible to complete passes through confirms and carries out the simple design thoroughly.
Xilinx has developed the many kinds of process pre-tests the new video frequency IP module group, we only need drag and drop and drop the module in System Generator to be able with ease to construct our video frequency/image system. This has saved the precious time for the development personnel, causes them not to need to use the HDL language to compile these basic modules again the code.
In order to process by the development board sends out the PC machine massive video frequency data stream, System Generator for DSP also introduced another kind of new high speed hardware coordination simulation (to realize through an ethernet connection). This connection may realize the high current capacity under the low detention, the fact proved that this environment constructs time the video frequency/image system in System under the Generator is useful.
Xilinx has also promoted another section based on MATLAB the language design tool AccelDSP synthesis tool, this is uses on Xilinx FPGA designing the DSP module the high-quality tool. It may complete the floating point automatically to the fixed-point transformation, produces VHDL which or Verilog code may synthesize, and founds one to test the platform to use in confirming. We may also act according to a section of MATLAB algorithm to produce a fixed-point the C model or System the Generator module. AccelDSP is Xilinx in the XtremeDSP plan essential module, but Xilinx XtremeDSP was a set unifies most advanced FPGA, to design the tool, the IP nucleus and the partner relations as well as the design and the training service plan.
This article subtotal
In a video frequency supervisory system, the video signal is produces through many photograph cameras. The FPGA function is the receive form digital video signal and will process after video frequency encoder’s ITU-R the BT656 the video data delivers on the monitoring device the demonstration and delivers to the digital media processor or DSP carries on the compression, and saves to the hard disk.
Uses Xilinx FPGA, the customer can realize in its compatible standard system with the competitive product difference, simultaneously still could obtain in view of the application best balance point. But had the video frequency IP module group which Xilinx provides, the customer can with ease construct the DVR system which is highly nimble and may adjust, with the aim of simultaneously satisfying the low end and the high-end market demand. In Xilinx FPGA provides the VLYNQ essence can let the customer with ease the massive video frequency data stream which sends in many cameras transmit to the TI Da Vinci processor carries on processing.
AccelChip and Xilinx System the Generator these two kind of tool’s integration simultaneously has given dual attention to the algorithm development personnel by chance constructs the teacher and the hardware designer presente in figures and diagrams design cycle by chance based on the MATLAB algorithm comprehensive development way and the system, therefore the designers may use the rich MATLAB language and the supplementary toolbox found complex DSP algorithm System Generator the IP module. Through uses these tools, the design group can use the most highly effective hardware modelling way to carry on the design to realize, and lets the algorithm development personnel comprehensively participation in the FPGA design process, thus realizes the high quality design quickly.
