Abstract: This article has analyzed the present 8 micro controller’s renewal and the design tendency, mainly discusses its RISC system construction the product design, and key from system construction angle embarking, on the high performance, the low power loss two aspects to the key technologies which used in the design has conducted the discussion research.
Key word: RISC; Micro controller; Low power loss; Assembly line
Abstract:The existing 8-bit microcontroller’s renewal and design tendency is analyzed in this paper. Its product design of RISC architecture is also mainly discussed. Focusing from the point of architecture, discussion and investigation is carried out on essential technology about high-performance and low-power used in the design too.
Key Words: RISC; Microcontroller; Low-power; Pipelining
1. introduction
Micro controller (Microcontroller) has appeared since the 1970s, will be near in 30 year to obtain the swift and violent development and the widespread application. Along with microelectronic technology’s swift development, the micro controller is good by its performance, the volume is small, the price is superior, the function complete and so on prominent merit is widely applied in domains and so on domestic electric appliances, computation and peripheral device, communication, industrial control, automated production, intellectualized equipment as well as instruments and meters, becomes the scientific research, the teaching, the industrial technology to transform the most efficient tool. From uses the Princeton structure to use the Harvard bus structure generally at the first simple micro controller to the present the RISC micro controller, the micro controller has obtained rapid development [1].
8 micro controllers are the present application quantity biggest micro controllers, is also the market which at present most companies devote to do farm work; Its market and the price competition extremely is intense, each kind of multi-purpose demand as well as the different specification’s product weeds through the old to bring forth the new the speed extremely is also fast. Along with the integrated circuit and the semiconductor processing technology’s fast development, FPGA and the SOC technology competes unceasingly and fuses, electronic products’ design is better to the system performance, the power loss to be smaller gradually, the cost to be lower, the reliability to be higher, to develop a easier direction to develop. Therefore, promoted rapidly conforms to the market demand high performance-to-price ratio, the low power loss, the high economic efficiency 8 micro controller chip or IP Core has become the hot spot which nowadays many companies compete chase.
2. present 8 micro controller’s renewal and design tendency
Regarding different micro controller (MCU) product application, not only needs to consider different factory MCU the performance-to-price ratio, moreover also needs to consider under the different command system the MCU application characteristic. In view of new intellectualization electronic products which emerges unceasingly, the people have been developing suit in different embedded system application MCU new product [2]. Different factory’s MCU product its set of instructions is various, specially set of instructions system construction difference, if in the market the widespread application’s MCS51 series and the PIC series micro controller separately uses the CISC command system and the RISC command system.
The micro controller may divide into CISC, RISC, kind of RISC according to the command system (RISC-LIKE) and so on several kinds. The traditional MCS51 controller belongs to CISC, its code density is high, but the majority instructions need many clock cycles to complete. The RISC general instruction density is low, but the instruction efficiency is very high. Kind of RISC has at the same time CISC and the RISC merit. The reason that RISC and kind of RISC have the so high instruction efficiency, benefits hard wiring structure which and running water line structure brings in the small set of instructions. The simple set of instructions may use the hard wiring to carry on the instruction decoding, but does not need to use the micro code control the way, raised the decoding efficiency. The running water line structure divides into the instruction several steps to complete, when assembly line stuff work, each instruction average execution time (CPI) about 1 clock cycle [3]. Generally speaking, RISC wants quick 50% compared to same level CISC–70%, are simultaneously easier to design and the error correction.
Therefore, to 8 micro controller’s product developments and the research design was mainly at present take the compatible market in already the product which is widely used by the customer as the premise, enhanced the performance unceasingly and reduces the power loss to adapt the market competition and the technological development. Regarding is the CISC command system’s micro controller product originally, in emerges one after another incessantly in renewal series already fusion RISC thought gradually; Regarding used the RISC command system’s micro controller, more procedures were still aim at the high performance low power loss the demand to carry on the optimization and the improvement unceasingly to its entire system construction, particularly the running water line structure’s improvement saw most much. This article is precisely under this kind of situation proposed that mainly discusses the RISC system construction 8 micro controller product design technique.
3.RISC microprocessor’s structural feature and principle of design
Although the present field should have any characteristic to the RISC processor also to have the different view, but each kind of RISC structure has some general character [4]:(1) to use the Harvard bus structure, the majority instructions complete in a clock cycle are advantageous realize the structural flow hydration; (2) uses independent and the simple loading/memory structure; (3) instruction decoding usually is the hard segment realizes, but is not the micro decoding, with the aim of speeding up carries out the speed; (4) most instructions have the fixed form, simplifies the command code and the decoding; (5) small set of instructions and minority several kind of addressing mode; (6) data channel assembly line, causes the treating processes highly parallel; (7) uses the large capacity high-speed register to pile (or is called register file), avoids as far as possible with the speed low system RAM exchange data. As far as possible the operational data will deposit in the register, thus reduced visit memory number of times. According to the above discussion, as follows key from system construction angle embarking, on the high performance, the low power loss two aspects has conducted the discussion research to 8 RISC micro controller’s in design key technologies.
4. key technologies
4.1 RISC set of instructions selection
The controller system’s use is closely related with between the software programming and hardware design’s specification connection, this connection is the micro controller’s set of instructions. The instruction architecture (ISA) is carries on the microprocessor software and hardware coordination design the premise. The set of instructions must be complete, enables the function which all may calculate in the reasonable procedure space to realize; Moreover the set of instructions must be highly effective, with the aim of enabling the commonly used function to be possible to use the relatively few instructions to realize. Therefore, provides for the application software development micro controller system must have one complete and the highly effective set of instructions.
The set of instructions decided directly the micro controller’s internal hardware architecture, simultaneously is also the user program translation production target code basis. The set of instructions is definite finally the program memory which, the data-carrier storage, the register variable and the memory addressing system and the overall system needs close related, and restricts mutually. Each part and even the concrete byte should have the only address, so that the set of instructions can correctly carries on the identification operation to each part or the byte. Therefore also had correspondingly a series in view of the different product different measure: the register which 1) from needs the address size which and increases correspondingly to measure the instruction the length; 2) carries on the classification to the instruction and determined separately each kind of instruction byte format, simplifies the work management signal the decoding logic; 3) increases the corresponding register to make up the instruction byte length the insufficiency; 4) the instruction byte format assignment should consider the corresponding part’s structure order of complexity and the corresponding addressing system; 5) memory, register, I/O mouth whether unified addressing. The above enumerates is not exhaustive also does not have successively division the smooth, should simultaneously carry on the analysis. The corresponding measure corresponds the performance, the power loss, the design order of complexity are respectively dissimilar, should unify the consideration.
Carries on the power loss analysis to ISA should considered from the instruction-code capacity and the instruction execute efficiency two aspects. Technical and so on set of instructions size, register variable, memory addressing system, running water line structure designations have the close relation with the instruction-code density. The research discovered that increases some specific complex instructions in the RISC simplification set of instructions is suitably enhances the code density, the guarantee processor high performance, the low power loss feasible method. Can therefore produce the high instruction-code density set of instructions is without doubt RISC low power loss design first choice [5].
4.2 have the paging design which the sharing area’s register piles
The RISC design concept’s most main feature is all operations faces the register. Using register—The register operates the instruction carries on the data transfer, sped up the speed, moreover also simplified the command control logic, reduced the hard wired logic constitution control portion’s chip area.
The fixed register address’s figure limits register’s quantity inevitably in the instruction, but the introduction high-end processor’s partition, the paging design concept may expand the addressing the scope. The partition, the paging design concept’s essential starting point lies in memory’s linear address decomposes two-dimensional or the multi-dimensional address; Only expresses in the instruction most lowers the Uygur address, but uses other facilities (for example section number register, page number register) to use for to deposit the high Uygur address. Generally piles the register divides into certain pages, each page has the fixed size, only uses in register’s page in the instruction the address. Establishes a page number register in the system special-purpose register, through changes its content to cut visit to different page register’s [6].
In order to overcome in the pure paging mechanism each kind of flaw, usually uses has the sharing area paging design, like this not only reduced in the instruction the register logical address figure, moreover can visit the system register at any time, simultaneously is advantageous for between the different page register through the sharing area in general register exchange information. Certainly must have the corresponding logical address to the physical address mapping method measure.
4.3 procedure space paging design
Because piles the similar reason with the register, in instruction, if uses the complete procedure space address, also will limit the procedure space size, therefore also has usually used the paging design concept to the procedure space, simultaneously has established the public procedure area in the different page (, if command length will meet procedure space address requirement completely, will then not need this thought), its design concept will be similar in having the sharing area register paging design, will no longer give unnecessary detail in this. What only and the register public area is different: The procedure public area is skips for the procedure between the different page provides the platform.
4.4 assembly line technologies
The assembly line design is inseparable with 8 RISC micro controller system construction, is overall system’s design core, it selects the fit and unfit quality immediate influence to system’s performance and the power loss.
The assembly line technology could maximum limit use the micro controller resources, caused each part to work in each clock cycle, raised the efficiency greatly, but because between assembly line each section had the very strong dependence. If processes improper, the instruction movement will not be able to achieve the anticipated result, must therefore know very well the assembly line related and the shift question. First is the resources conflict, as soon as namely the same time internal struggle with the identical functional unit, to simultaneously the reference to storage, this needs to stop generally pats the assembly line; Its two for the data correlation conflict, have three types: As soon as RAW, WAR, WAW, solve this conflict use interior to go nonstop to the structure or the detention pat the assembly line; Its three for the control transfer conflict, namely regarding the condition skipping instruction, according to the operation result judge whether to skip, can determine the new PC value, the operation result is after the execution phase obtains, this causes the assembly line to lose many performance, generally uses increases the hardware to be solved operation result should in advance to conflict [3].
More is the long assembly line, is related and shifts two major problems to be also more serious: On the one hand causes the hardware control electric circuit complex degree to increase greatly, on the other hand, as a result of the assembly line metre’s stop, causes the CPI value enlargement and the system performance drop. Therefore, the assembly line is not longer is better, found a speed and the efficiency balance point is most important.
In 8 RISC micro controller’s assembly line design, the existence are very many a kind of plan. The different plan corresponds the area, the speed and the power loss are various. Concrete selects, then should fuse the consideration from many aspects. First should by system’s working speed request and the assembly line progression, the depth infers the strict succession which many kinds of concrete running water line structure plan and needs; Then from system’s power loss, the area, the performance and aspects and so on design order of complexity which causes by the running water linear dependence and the shift question considers to embark, judges various plans the fit and unfit quality; Finally the compromised choice tallies synergy.
4.5 low power loss technologies
Along with the semiconductor industry’s rapid development, the integrated circuit enters the deep submicron stage, microprocessor’s clock rate and the chip integration rate enhances unceasingly, the power loss has become the most important matter of concern in many design domains, what this is most prominent is the high performance microprocessor and portable electronic installation product [7].
In the basis system function showed when carries on the software and hardware coordination design, the determination instruction architecture, the different design starting point causes the design power loss result difference can be very big. Therefore the entire system construction’s determination is the most important question which without doubt the low power loss question should consider, mainly manifests following several aspect [5]:1) as far as possible according to the function demand optimization set of instructions, the simplified system’s decoding unit and the execution unit; 2) through develops hardware’s parallelism as well as the function unit running water execution realizes the low power loss structure; 3) the reasonable establishment determination memory, register’s capacity, reduces the main line number which needs; 4) on system hardware’s each submodule division as well as the software establishes the different active status to be important to the power loss optimization.
5. concluding remark
In micro controller application domain widespread today, proposed day by day to the micro controller a higher request, hoped the speed is quicker, the power loss to be lower, the low in price, easy to study Yi Yong as well as to compose time system’s periphery component to be less. Therefore, appears to the present application quantity broadest 8 micro controller’s product development and the design research especially important. Also the architecture design is key of the entire design key, after that all work, rely on the architecture which designs carry on. The question which to 8 RISC system construction in this article in light of this uses the key technologies which should consider to carry on the analysis and the discussion, has certain research value and the significance.
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