Because looks like American union tactic radio system (JTRS) such plan, software definition’s radio (SDR) was already confirmed. However, many questions are restricting the SDR widespread deployment seriously, the quite important question is a power.
The power is in designs time each SDR subsystem’s main consideration factor, because specially they must consume the hardware are radio than more powers. For example, to obtain the anticipated radio traffic to be away from (relies on link condition, typical value is 5-10 kilometers magnitudes), front end radio frequency (RF) must have the enough emissive power. Similarly, regarding depends on the battery work the wireless apparatus, front end RF, the modem and the encryption processes subsystem’s power loss immediate influence wireless apparatus’ life. In addition, to the quantity of heat which produces by the modem carries on the radiation the ability immediate influence to wireless apparatus’ life, and even possibly affects to can in the engine case the simultaneous working channel number, and has more influences.
Therefore, reduces SDR the power to have many advantage, these advantage possibly even include through purchase less battery backups to reduce the operation expense. Here, to obtain some advantage, we will discuss will place with emphasis reduce the SDR modem power loss in the overall method.
Reduces the power loss the hardware method
In order to reduce in modem’s power loss, most people first pay attention are in the treating processes hardware, usually contains scene programmable gate array (FPGA), digital signal processor (DSP) and general goal processor (GPP). Differentiates any hardware component’s two power loss source - - static state power loss and the dynamic power loss - - is very important. The static power loss was one added the inherent power which the electricity but inactive component consumed, controlled by transistor’s electric current divulging. On the other hand, the dynamic power loss is the power which consumes by the active use’s components, this power receives certain variables the influence, including supply voltage, to the exterior memory’s access, data bandwidth, and so on. Examines two types the power losses is very important, specially in the wireless apparatus have a usual receive emissivity longer to account for spatial cyclical under the situation. In GPP and even under the DSP situation, the image frequency adjustment, the voltage regulation and the power source closure pattern such power source management function already became day by day universal. However, what situation about FPGA is also?
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| Figure 1: Uses in reducing the SDR power loss one true overall method to use from each quadrant many kinds of technologies. |
Many methods may use for to reduce in FPGA the static state or the dynamic power loss, many methods are not may simultaneously apply. Some reduce the static power loss the method including three extremely grid oxide layer power source gating.
Using three grid oxide layers, the silicon supplier covers an oxide layer on the transistor to reduce divulging extremely; The overburden layer is thicker, divulging is smaller. The performance maintains balanced. Needs the performance in the essence the place, common uses the thin oxide layer; But regarding actuation high voltage’s I/O, must use the thick oxide layer. In does not need the biggest performance the place, if disposes SRAM, the additional middle oxide layer may reduce divulging enormously. Using this kind of technology’s FPGA example Virtex-4 which and the Virtex-5 series thinks including the match spirit.
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| Figure 2: Has the power observed value to be possible to simplify based on the pattern layout flow to the profile division decision-making. |
When the FPGA module has not been used, the power source gating involves transistor’s use to reduce waits for an opportunity divulging. This kind of technology’s example may see in the low power loss sleep pattern. For example, if in a FPGA all module by power source gating, this component consumes the very small static power loss. Under this situation, what is balanced is the FPGA disposition loss, so that this component is awakening process period by the reshuffle, this process possibly must spend several milliseconds completely. On the other hand, has the disposition module besides these (for instance to dispose memory), if all modules by power source gating, that the FPGA condition maintained. Although awakened the time to reduce enormously, but, saved the power was inferior by far worked as all modules by the power source gating was such remarkable. The match spirit thinks Spartan-3A series FPGA supports two types the power sources gating.
The dynamic power loss is power equality other part. Reduces the dynamic power loss the method including the processor integration, the special-purpose IP module and the clock gating.
Regarding had embedded GPP and DSP engine’s platform FPGA, the processor integration was very useful. Through uses embedded GPP, but is not separate GPP, does not need to actuate the data to surmount the exterior I/O line from FPGA (to surmount exterior I/O line usual consumption massive powers) to GPP, thus saves the power. Virtex-4 the FX component is a platform FPGA example.
Let the special-purpose IP module carry out certain common functions to be possible to reduce the dynamic power loss enormously, but actually does not have the major impact on the flexibility. An example is lets in FPGA the special-purpose engine carry out the multiplication - - sum function. With uses the plan which the logic circuit realizes to compare, this kind of special-purpose IP module can by be higher much performance to carry out that function and the province electricity above 85%. The Virtex-5 component has including the DSP engine, Ethernet MAC and PCI Express vertex many special-purpose modules, causes its to be possible to provide the advanced function by the low power loss.
The clock gating technology uses the FPGA module clock which the electric circuit shuts down does not use, thus reduces these module’s power loss to leakage current quantity. If Virtex-4 and Virtex-5 such FPGA are supports this performance the best model.
Because reduces the static state and the dynamic power loss is very important, looking from the hardware to both’s influence, the most powerful method further reduces the supply voltage. One of best examples further reduces the essence voltage. Processes the component to shift along with them to the next generation craft node (is also from 90nm to the 65nm shift) tends to profits from the low voltage. For example, the 65nm Virtex-5 FPGA essence voltage is 1.0V, compared to work in 1.2V 90nm Virtex-4 FPGA low 17%, compared to work in 1.5V 130nm Virtex-II FPGA low 33%. This uses one of majority current component’s advantage. The low essence voltage has the major impact on the static state and dynamic power loss both, because divulging and the voltage assume the index relations, but the dynamic power loss and the voltage assume the quadratic side the relations. Therefore, Virtex-5 component compared to Virtex-4 FPGA static state and dynamic power loss average low above 30%.
Above we discussed reduced in SDR the power loss certain hardware method, these methods were important, but, felt that has lacked some contents likely. After all, this is not been called radio the software definition? Although project engineer is willing to provide the discussion to the hardware about to reduce their component power loss question, but, the reality is software engineer who many so-called “the hardware company” has must be more than hardware engineer. Truly, this as if indicates reduces the power loss is not only hardware’s matter.
Reduces the power loss with one more overall method
Yes! Indeed existence true optimization SDR the power loss method, project engineer needs one kind the more overall method which unifies the hardware and programming technology both. One kind of invalid execution’s profile possibly has the huge negative influence to the SDR power loss, no matter the hardware design has how well! Project engineer may use many technologies to realize a profile effectively in FPGA, these technologies including parallel processing algorithm, low frequency operation, power first floor plan and partial disposition.
Uses the parallel processing algorithm, the parallel processing ability which FPGA provides allowed that realizes looks like the performance which DSP or GPP such serial processor possibly achieves to be higher than much the signal processing performance, this already obtained the very good confirmation. Because the parallel processing may use the serial processor is lower than much the clock rates to carry out the task, when uses the parallel processing algorithm time, FPGA is in fact higher than the processor energy efficiency.
Uses the low frequency work, many military profiles can from the movement, in the low frequency reduces in the power loss to obtain the advantage. What is common is in the FPGA profile is lower than 200MHz the frequency movement, is lower than the biggest frequency by far.
The above some technical like clock gating use to designs carries on some careful first floor plan to be possibly more effective. For example, to use the clock gating superiority truly, project engineer wants to use the same clock to obtain a design several part, but this clock may in the same region - - perhaps in component’s 1/4 quadrants - - gating. At present in the market condition may the use tool like match spirit think the PlanAhead design and the analysis tool cause the first floor plan using graphical user interface (GUI) become easier.
Partial reshuffle (PR) allows project engineer in FPGA fixed time multiplying each resources. If does not have PR, project engineer possibly can not but heavy load entire FPGA support a new profile pattern, therefore, loses the information link temporarily, or lets all patterns also write down in big FPGA, even if one time uses a pattern merely. PR allowed that supports the multi-pattern profile, does not need simultaneously to write down all patterns in FPGA, therefore, can and the low power loss realizes the same function by small FPGA. Uses PR effectively also from the first floor plan benefit. Is similar in the low essence voltage, PR can affect static and dynamic power this both, but, the above technology merely affects the dynamic power.
Figure 1 described these to use in reducing the power loss each method. Uses in reducing the SDR power loss one true overall method to use from each quadrant many kinds of technologies.
The supposition has many uses in reducing the SDR power loss the method, many methods may combine, as if does not have what opportunity to be able to determine that the ideal power optimization profile realizes the plan. Increases place of the confusion lies in: Many profile ingredient like forward-acting error correction (FCC) can frequently realizes effectively in the middle of FPGA or on DSP any. Usually what is not clear: How carries on the best division between the hardware and the software to realize the energy efficiency maximization? Although does not have the panacea, namely does not have any kind of tool to be able to evaluate all different options and the transformation by decisively the distinction optimization solution, but, has certainly one kind compared to guess purely better method, what this kind of guess with was already the data sheet digit which and based on the electronic data sheet’s power estimate published.
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| Figure 3: The power monitors GUI demonstration modem FPGA and the DSP power dissipation, eliminates realizes the power dissipation guess to the profile. |
Eliminates guessed: SDR power optimization test bed
One finer method is visits one to use in the power optimization design being able to take tests bed’s SDR. Had this kind of kind of test bed, allowed that project engineer or the system construction teacher carries on the test according to the experience, and measures and the specific hardware and software design related compromised for the power optimization design. Project engineer possibly not only need compare above discussion’s some good and bad points, moreover possibly must relatively with ease develops and divides a profile repeatedly between FPGA and DSP/GPP, at the same time, gathers the power observed value on each modem processing component.
Although is nonessential, but, uses based on pattern layout each concept, carries on the modelling through one visual way, may also divide by way of the profile provides each kind of advantage. This kind of kind of design cycle’s example see Figure 2. In this example, may use MathWorks Corporation’s Simulink to carry on the modelling. Project engineer may choose between available FPGA and DSP carries on the division to the profile and realizes directly on the hardware, realizes the process to want to think using the match spirit uses in DSP System Generator and uses in FPGA ISE the Foundation design tool suite, as well as MathWorks Corporation’s Real-Time Workshop and TI Corporation uses in DSP Code Composer Studio.
Project engineer may also use in based on model design environment one kind of Power Monitoring GUI, take the real time display as the power observed value which FPGA and DSP record independently. A such GUI example see Figure 3. This kind of record ability allowed that project engineer makes to the profile along with time variation’s energy efficiency has the basis decision-making, is not only the prompt snapshot profile. This is essential, because many profiles are essentially “arise suddenly”. If the profile realizes causes the modem to surpass the power budget the situation becomes obvious, project engineer may return to the model and aim at a better efficiency to divide to the profile. Although this flow by no means is now easy, but, this kind of endeavor is worth, when it eliminated carries on the estimate to modem’s power loss the guess.
Thinks, TI and the Lyrtech cooperation through the match spirit, such one kind had power monitor SDR the test bed already to start to supply goods. This small shape factor’s SDR develops the platform unifies Virtex-4 FPGA and DM6446 DSP/GPP, thus lets project engineer be able to carry on the low power loss design.
In order to reduce the power loss to design
Although in the tradition has placed the key point reduces in the SDR hardware’s power loss, but, the software also has the major impact obviously to the power loss. Because of so, is needing one overall method to reduce SDR the power loss. Moreover, can actual play the SDR role the test bed to be helpful in eliminates to this question guess. Although this method possibly must carry on more plans and the development in advance, but, the advantage is the force and enables the SDR provider, in provides the scene duration to be longer, reliably, and in needs little in battery backup’s wireless apparatus process to establish the competitive advantage.
