How does the abstract discuss designs, manufactures one kind to plant electric cable - - USB-blaster under the low cost usB data which QHattusII under the programer environment uses. According to the IEEEll49.1 standard, the USB agreement as well as the JTAG boundary scan principle, through analyzes the QuartusII internal communication mechanism, uses the USB chip and the CPLD union, proposed that one kind of USB interface circuit design with realizes the method. With traditional and the mouth, the serial port downloading electric cable compares, it has the very big superiority on the downloading speed and the flexibility.
Under the key word plants electric cable USB CPLD FPGA ISP JTAG
Introduction
Along with piece on system (SoC, System on Chip) time arrival, including complex programmable logical component (CPLD, Complex ProgrammableLogic Devi(e) and scene programmable gate array (FPGA, Field Programmable Gate Array) the programmable logical component (has unique merit which may program again in system), the application is getting more and more widespread. This for used in the programmable logical component programming the downloading electric cable setting a higher request.
This article studies based on IEEEll49.1 the standard USB downloading interface circuit’s design and realizes. In view of Altera Corporation’s FPGA component Cy-ckone, through analyzes its boundary scan test structure and each kind of JTAG instruction, studies its programming process and the programming characteristic, and proposes the design proposal. In the interface circuit hardware design, selects FTDI Corporation’s USB control chip FT2 li BM, realizes the USB physics level and the link level agreement analysis; Altera Corporation’s programmable logical component EPM7064 realizes the interface logic. Compares with the tradition based on PC and the mouth downloading electric cable, this design’s USB downloading interface circuit has supports inserts hotly slightly pulls out, the volume, to be advantageous carries, reduces quickly to the PC hardware injury, the programming speed and so on obvious merit.
At present has developed the USB downloading line needs generally, in the main engine end designs the software to control and between the downloading line and the goal component’s correspondence and the data transfer separate; But like this not only tedious, moreover possible different to affect the compatibility as a result of the PC machine operating system. This article discusses the USB downloading line can in A1tera under Corporation’s QuartusII development environment the direct use, does not need in the main engine end separate design correspondence software.
1 system structure and principle of work
Interface circuit’s overall construction diagram like chart l shows. Because the USB downloading electric circuit has involved the IEEEll49.1 standard and the USB agreement, therefore the interface circuit mainly contains two major parts. A part is the USB connection, it connects the main engine and the programmable logical component, the major function is carries on USB and between the parallel I/O mouth data format transforms, controls the chip with USB to realize. Another part is the JTAG connection, it connects the logical component which the USB control chip and needs to program, the major function is carries on between the parallel I/O mouth and JTAG the data transformation, transformation logic through carries on the design to the programmable logical component to realize. Other also include some essential clock circuit and the voltage switching circuit.
USB data which transmits from the main engine, by the USB control chip transformation is 8 bit parallel data, delivers CPLD after the data bus the programmable I/O pin. The CPLD data may also return to the USB control chip through the data bus, then the transformation is the USB data format feeds in the main engine. After CPLD receives the data which the USB control chip transmits, carries on the analysis to the data, then transforms to conform to the IEEEll49.1 standard programming data and the instruction, from TCK, TMS and the TDI serial output to the programmable logical component which must program. Returns from the programmable logical component conforms to the IEEEll49.1 standard verification data from the TDO serial input to CPLD, the transformation is 8 bit parallel data transfer for the USB control chip, finally returns to the main engine to carry on the verification.
USB control chip FT245BM is responsible to explain the USB agreement, completes both sides data communication. Its interior has the USB agreement engine, and integrates the level switch causes FIFO and the control signal can with the voltage be 5 V, 3.3 V logical component connection. USB interface circuit principle as shown in Figure 2.
2 pair of goal component’s disposition process
To goal component’s disposition flow as shown in Figure 3.
(1) distinguishes the USB downloading connection
The Quanus II programmer sends 7e, 7f, the 7c three data in turn through the PC USB connection to FT245BM. FT245BM returns to 3 data in turn after the PC USB connection to the programmer 03. After the programmer receives the returns 3 03, the programmer distinguishes this USB downloading interface circuit for its downloading hardware platform.
(2) tests the BST electric circuit
Test including the following several aspects:
◇ replacement test;
◇ the instruction register shifts the test;
◇ symbolized that the register shifts the test.
(3) downloading programming data
This step downloads all programming data from PC the programmable logical component’s disposition memory. Because this step downloading programming data is huge, therefore time downloading uses the express pattern, and does not carry on the verification, avoids affecting the downloading speed. Downloading selects the instruction is the DOWNLOAD instruction which Ahcra Corporation define (00 0000 0010).
in (4) constructs from the test
In constructs from the test is in the electric circuit the establishment test generation, exerts, the analysis and the test control structure, enables the electric circuit to be able to test itself.
(5) verifies component’s IDCODE
Before the entire programming flow conclusion, again verifies component’s ID-CODE, confirmed component’s BST electric circuit after downloading programming data otherwise works fully normally. This step process and the sign register shifts the test to be completely same.
(6) returns test logic reset state
Maintains TMS is the high 6 TCK cycle, causes the TAP controller to enter the test logic reset state, and lets TMS maintains for the high level, maintains the test logic reset state. Such component’s test logic expires, component’s core logic starts the normal work.
Conclusion
This article discusses the USB data downloading line can in Altera under Corporation’s QuartusII development environment the direct use, does not need to develop the main engine end signal procedure separate. Compare with the tradition and several programming ways, the superiority is very obvious: Supports inserts hotly pulls out, the use is more convenient; The volume is smaller, carries conveniently; The programming speed is quicker, save time. Emerged vigorously for the international number system design domain in online programs the (ISP) technology the promotion and the development has provided the powerful support.
