Abstract many monolithic integrated circuits through the serial total dimension serial interface (I2C, SPI) the memory chip may constitute simple and direct, the highly effective multi-main engine system. The multi-main engine system needs to solve uses in common the serial main line’s arbitration question, this article gives use first encoder 74HCl48 and decoder 74HCl38 realizes the hardware arbitration solution. Realizes the bus arbitration with the software to compare, this method simple reliable, timeliness is high, may realize main line’s appointment function, is suitable in by each different type CPU constitution multi-computer system, further enhances the multi-main engine system’s performance.
Key word multi-main engine system serial main line I2C SPI hardware arbitration first encoder
Introduction
Along with the monolithic integrated circuit technology’s development and the monolithic integrated circuit chip price’s drop, uses many same types or the different type monolithic integrated circuit constitutes more than a monolithic integrated circuit system, may obtain the good system flexibility and the performance price compared to, if may use a AT89C52 monolithic integrated circuit to make the multi-purpose periphery component chip. In the system between many monolithic integrated circuit’s correspondences may have many kinds of ways, like hardware UART, internal SPI/I2C main line, software simulation SPI/I2C main line, I/O mouth, pair of mouth RAM and based on the I2C main line and FRAM mailing address. And, based on serial main line (SPI either I2C) and serial interface memory chip (FRAM or SRAM, like in DSl302 chip SRAM) the mailing address is one kind simple, highly effective, the practical solution. This time, the system may have many main engines, needs to solve the serial main line’s arbitration problem, namely only allows a main engine in some time to take the serial main line. In reference [1] and [4], uses the test sequence and the time piece software arbitration method separately realizes, needs to take CPU the process time, and has the possibility in the arbitration process to receive the exterior disturbance, therefore has the high request to the software programming’s reliability. This supposes
Counts use first encoder 74HCl48 and decoder 74HCl38, carries on the bus arbitration through the hardware way. Causes the arbitration to need the time is greatly the reduction, the reliability has the enhancement.
Below take the n=8 main engine system as the example explained emphatically the serial bus hardware arbitration realizes the method, and promotes it to the n>8 multi-computer system.
1 decoder 74HCl38 function synopsis
74HCl38 is the very common three 18 decoders. This decoder has 3 to input A2, Al, A0, they altogether have 8 condition combinations, may translate 8 output signal Y0~Y7. In the 74HCl38 truth table which arranges in order from Table 1 may see: When STA, STB, STC are dissatisfied enables the condition, the Y0~Y7 output is 1, is the invalid signal; But when 74HCl38 enables the condition satisfiedly, Y0~Y7 one is 0, namely has a group desired signal (by A2, Al, the AO decision), other are 1. (74HCl38 pin arrangement see also Figure 1)
2 first encoder 74HCl48 function synopsis
74HCl48 is eight 13 first encoders. This encoder has 8 signal input ends, 3 binary code out-port. In addition, the electric circuit also established the input to enable to carry EI, the output enables to carry EO and the first encoder active status to symbolize GS. In the 74HCl48 truth table which arrange in order from Table 2 may see: When EI=1, no matter 8 input end why condition, 3 out-ports are the high levels, and outputs enables the end and the status flag end is the high level, the encoder is at the shut-down condition; When EI=O, when has at least an input end has the code request signal (logical O), GS is 0, indicated that the encoder is at the active status, otherwise is 1. May know by the truth table, in 8 input end not low level input signal and when inputs the O end (first rank most low position), A2AlAO is 111, this time may distinguish by the GS condition. When GS=1, expressed that the non-input signal, A2A1A0=111 is the non-code output; When GS=O, A2AlA0=111 expressed that the response inputs the O end for low level time code output. E0 only then in EI is 0, and all input ends are time l, the output is 0, uses in the cascade.
May know by Table 2, the input first rank’s order in turn is 17,16,15,14,13,12,11,10. Inputs the desired signal is the low level, when some input end has the low level input, and compared to its first rank high input end not low level time, the out-port only then outputs input end’s code which corresponds; At the same time, the 74HC148 code output is a radix-minus-one complement. For example, when 17 are O, the code output is 000. (74HC148 pin arrangement see also Figure 1)
3 hardware arbitration realization
May realize 8 main engine’s hardware arbitrations using 74HC148 and 74HCl38, circuitry as shown in Figure 1. This electric circuit (for example FM24C64) takes the data exchange chip by the I2C main line chip. The electric circuit provides 3 types the signals: Ask, Reply, Status. Ask is the bus request signal, Reply is the bus request inverse signal, Status is the main line condition. May know from Figure 1, the Ask effective request signal is the low level. When Ask0~Ask7 for high level, the GS(Status) output is the high level, this time 74HCl38 is at the invalid active status, Reply0~Reply7 is the high level signal. When in AskO~Ask7 at least some low level, the GS(Status) output is the low level, causes 74HCl38 to be at the decoding condition, Reply0~Reply7 has a low level output at least, therefore Starus is the low level expressed that the main line is taken.
Each main engine needs to provide 3 I/O mouths uses in the bus arbitration as the pilot wire and the condition line, 2 I/0 mouths use in the read-write I2C main line.
Take CPUA as an example, when CPUA needs to take the main line, first inspects Status the condition, if is the high level, explained that the main line has not been taken, if is the low level, explained that the main line has been taken; When CPU has not taken the main line, CPUA may send out the main line application signal (to set Ask0 for low level). This time, also has the possibility to have many CPU simultaneously to send out the main line application signal, but only then first rank highest CPU applies effectively. Therefore, CPUA inspects Reply0 immediately the level, if is the low level, then explained that applies for the main line successfully, may carry on the data manipulation to the I2C main line; Otherwise, the main line is taken by other CPU, needs when Status to be the high level continues to apply.
Take Figure 1 as an example, the CPUH priority is highest. What must explain, because the 74HCl48 output’s code is a radix-minus-one complement, when 74HCl48 17 inputs for low level, the code output should be 000, outputs Y0 after the 74HC138 decoding is the low level. Similarly, 16 correspond Yl, ex analogia.
CPU after sending out the application, if does not have the success to obtain the main line, must abolish the main line application signal (Ask to set immediately for high level), will otherwise affect other CPU the main line application; If succeeds obtains the main line, after completing the data processing, must abolish the main line application signal immediately.
The related software programming is also quite simple, take the MCS51 monolithic integrated circuit as an example;
In software aspect, but also needs to the I2C chip (for example FM24C64,8 KB) the address space carries on the assignment. May according to need to give each main engine to assign a continual address space, the spatial size may different, for example CPUA obtains AddrA the address space. In AddrA, carries on the segmentation again, for example CPUC and the CPUA correspondence’s address is AddrAC. When CPUC needs to transmit the data for CPUA, only need read in the data AddrAC in the address, but by CPUA after obtaining the main line reads AddrAC the data, thus completes the data transfer the process. Uses the I2C chip to take the data chip, must guarantee, in each CPU has not obtained in main line’s situation, corresponding SDA and the SCL mouth line maintains for the high level.
Chart l may use in the main engine quantity is smaller than or is equal to 8 situations.
When main engine quantity is bigger than 8 (for example 16), may use 2 piece of 74HCl48 to realize 16 14 priority encodings through the cascade, simultaneously uses 2 piece of 74HCl38 to realize four 16 decodings through the cascade. Cascade method audience reference [5]. What must pay attention, after the cascade, some CPU Ask and Reply must be 11 correspondences.
4 main line appointments
Because 8 main engine’s request line Ask0~Ask7 has the different priority, when the system is high to the real-time performance requirement, may realize the main line appointment function through 3 pilot wires. This article take MCS5l series monolithic integrated circuit CPUA as example showing.
Method one: Passes through “must” the gate, after the Status condition line turns on CPUA external interrupt INTO or INTl (external interrupt establishes as drop along triggering), when after other high priority release main line, the Status end presents the drop along, causes CPUA to enter the interrupt, causes CPUA to be possible to obtain the main line promptly.
Method two: Meets Reply0 to CPUA external interrupt INT0 or INTl (external interrupt establishes as drop along triggering), when CPUA needs to obtain the main line as soon as possible, sets at AskO for the low level; After other high priority release main line, Reply0 namely becomes the low level by the high level, CPUA enters the interrupt, thus obtains the main line.
Conclusion
Compose the multi-main engine system’s hardware arbitration logic using 74HCl48 and 74HCl38, the electric circuit are simple, are reliable, the CPU process time is extremely short, stable property. The author has applied this technology in the actual data acquisition system, the systems operation is reliable. In the serial chip’s choice, the poss ferroelectric random access memory (the FM series) the storing velocity quick (I2C main line frequency may reach lMHz, SPI main line frequency to be possible to reach 25MHz), the write data does not have the time delay, the read-write number of times is 10,000,000,000 times, the low power loss operation, the capacity is big, may realize I2C and the SPI main line by the software simulation, suits each type the monolithic integrated circuit, is the very ideal memory chip.
