The abstract in view of the numerically-controlled machine tool control development’s in new request, proposes and designs one kind of new control plan. Realizes using the PCI main line with the DSP correspondence, raises the control efficiency and timeliness; Using CPLD solution pair of mouth RAM arbitration control logic question. After the hardware design completes, proposed the two-way communication software testing method.
Key word PCI main line CH365 pair of mouth RAM CPLD DSP
Introduction
Along with the numerical control technology and the equipment development, specially in the general microcomputer numerical control domain, by the PC movement controller pattern’s open style motion control system, already more and more brought to people’s attention. This open style numerical control system can move in many kinds of platforms, may operate alternately with other systems, and can provide one kind of unified style to the user the interactive mode; Has may the interoperability, the probability, scale all suitable and may characteristics and so on complementarity. The PC machine technology introduction motion control domain, has provided the recent development opportunities and the direction of advance from the software and the hardware aspect for the open style motion control technology.
DSP present already tends to be mature as the motion control component’s technology, and applies successfully during the actual industrial production. TMS320C2407 is American TI (Texas Instruments) the company specially one kind of low price which, high performance 16 fixed-point arithmetic DSP promotes for the motor control (DMC) application. This component the high performance DSP essence and the rich micro controller peripheral device function collection in a body, has provided for the control system application one kind of ideal solution.
1 hardware circuit overall project design
PC machine and between the DSP correspondence the quite commonly used method is through at present the RS232 serial communication, but this way speed is slow, and is unable to realize the real-time control, therefore considered that implements the transmission duty using the PC machine PCI connection. The PCI main line is one kind of high performance 32/64 bit address, the data multiplying main line, it is one kind of independent processor’s synchronous bus, may support sends the transmission broken. Its main line clock rate is o~33MHz. Issued the 132MB/s transmission speed in the 33MHz operating frequency. The PCI main line compares with other mainstream main line, the speed is quicker, timeliness is better, the controllability is better, is suitable for the high speed real-time I/O control card; But because the PCI main line agreement is quite complex, therefore its interface circuit realizes is not easy, but uses the general PCI connection chip to be able to solve this problem well.
At present in the market the common PCI bridge chip mainly has AMCC, PLX, CYPRESS as well as Nanjing seeps permanent electronic company’s serial productses and so on CH36X. According to the comparison as well as this system’s actual request, selects Nanjing to seep permanent electronic company’s CH365. This chip has the following characteristic: Supports the I/O port mapping, the memory mapping, to expand ROM as well as the interrupt. CH365 transforms 32 high speed PCI main lines into simple Yi Yong being similar in the ISA main line’s 8 driving parallel interfaces, uses in manufacturing the low cost based on the PCI main line’s computer board card, as well as will promote originally based on the ISA main line’s board card to the PCI main line on.
To this system, the PC confidential transmission control command and carries on the massive data computation, the data exchange should take the short machine-hour as far as possible and the few memory space. Moreover, between the PCI main line and DSP must carry on massively, the reliable data transmission, they many excessively take the CPU time, causes the CPU efficiency to reduce. The use pair of mouth RAM exchange information, both sides treat as it a oneself memory’s part, may guarantee high speed, the reliable data communication. This system selects CY7C133, can definitely satisfy the data transmission the request. CY7C133 is section of high speed 2K×16 position pair of mouth static state RAM, allows 2 (left and right) the port simultaneously to read/writes the data, each port has the independent control holding wire, the address wire and the data line. But the zero access data, the most low access time is 25ns, may with the majority high speed processor coordination use, but does not need to insert the waiting status. CY7C133 besides has the twin port access facility, but also has the marker function, when data transfer may constitute many kinds of connection forms.
2 interface circuit’s realization
2.1 pair of mouth only AM logical judgement
Double mouth RAM allows 2 CPU simultaneously to read any memory cell (including simultaneously to read identical address unit), as soon as soon as but does not allow simultaneously to write or reads writes the identical address unit, will otherwise appear reads in the value and the read-out value will not be the expected value troubled waters. Although the CY7C133 hardware itself has the BUSY control signal to be coordinated the both sides the visit, but the BUSY signal foot request and the both sides CPU READY line is connected, but CH365 does not have the READY holding wire, therefore, needs to introduce the arbitration logic control module. The commonly used pair of mouth RAM solution address competition’s way includes: Token transmission law, based on mailbox mechanism INT interrupt law as well as insertion waiting cycle BUSY law and so on. We use the 2nd method in this system.
Based on the mailbox mechanism’s INT interrupt’s method basic philosophy is: Assigns an address for each port to take the mailbox, for instance this system may use CH365 00H, DSP to use 8000H, these two addresses use for to load the achievement to assign two port RAM right of use the basis data. The concrete agreement is: When left port CH365 writes address unit 00H, may realize through the logical component interrupts DSP_TNT (the DSP interrupt) is low right, sends out the interrupt request to DSP, when DSP reads address unit 00H, DSP_INT is high, repositions interrupt request which CH365 sends out. When likewise, the right port writes address unit 8000H, left interrupts INT_REQ (the CH365 interrupt) is low, may the port send out the interrupt request toward left; But when the left port reads address 8000H, INT_REQ is high, repositions interrupt request which DSP sends out. When the mailbox content is 00, expressed uses this side port; When the mailbox content is FFH, indicated that the conclusion used this port. Therefore, both sides when carry on to port’s other units the read-write operation starts, needs to the mailbox to read in 00H; The operation ended, reads in FFH. If has not had the struggle to use, then carries on the read-write operation directly; Otherwise, a slow side has the interrupt, and inquires opposite party mailbox, until opposite party mailbox content is FFH. Realizes specifically may draw support from CPLD to complete.
2.2 main lines expand solution
The CH365 address bus width is 16, the data bus width is 8, the TMS320C2407 data bus and address bus’s width is 16, but the CY7C133 data bus width is 16, the address bus width is 11, therefore DSP and the CY7C133 connection and does not have the special place; But between CH365 and the CY7C133 interface circuit needed to carry on the main line to pair of mouth RAM to expand. The basic philosophy is realizes latch’s function using part CPLD, through to enables the signal the control, carries on the time sharing read-write 16 bit data, realizes data bus’s expansion, namely takes the hypothesized main line using the latch. Here selects EPM7032 CPLD to solve the main line to expand the question, its internal circuit like chart l shows.
Following discusses CH365 to the pair of mouth RAM read-write process. When CH365 carries on to pair of mouth RAM reads the data, the hypothesis this time A0 is the high level, this time 16 bit data read out from pair of mouth RAM, because high 8 bit data line and CH365 8 bit data line direct connected, therefore the high 8 bit data are read in immediately in CH365. At the same time, various signals’ mutual logical relation may obtain according to Figure 1, reads the latch (U1) enables signal G effectively (high level), OEN invalid (high level), thus the low 8 bit data are sent in U1 the lock to save. Then CH365 again carries on one time to read the operation, CH365_A0 turns the low level, double mouth RAM selects patches or strips of land as worth saving for seed the signal to turn the invalid level, therefore this time reads the operation not to have the influence to pair of mouth RAM, but this time U1 enabled signal G to turn the invalid level, but OEN turned the active level, previous time is locked the data which saved (i.e. the pair of mouth RAM low 8 bit data) to send in CH365, 16 bit data read off. When CH365 carries on the write operation to pair of mouth RAM, the hypothesis this time CH365_A0 is the low level, similarly may writes the buffer storage according to the chart l judgment (U2) enable signal G to be effective, but OEN is invalid, double mouth RAM selects patches or strips of land as worth saving for seed invalid, thus the data is locked exists in U2; Then CH365 again carries on one time to write the operation, because CH365_A0 turns the high level, double mouth RAM selects patches or strips of land as worth saving for seed effectively, U2 selects patches or strips of land as worth saving for seed invalid, OEN is the active level, when 16 bit data simultaneously read in pair of mouth RAM. May know from the above analysis, the use lowest address position CH365_AO different level, CH365 continual reads or writes the operation through two times, realized successfully the data read to pair of mouth RAM in or writes, but was time the read-in reads in high 8 first, latter read in low 8; But reads in reads in low 8 first, latter reads in high 8. At the same time, two piece of latches cannot appear at the same time the situation which selects. Will otherwise present the transmission data the confusion, will cause the transmission mistake.
This system’s hardware circuit principle (main part) as shown in Figure 2. As a result of TMS320C2407(3.3V) with the pair of mouth RAM(5V) level difference, has joined voltage transformation component SN74LVTHl6245A.
3 PCI and DSP correspondences
After the hardware circuit realizes, the board card which completes inserts in the PC machine PCI slot. After on electricity, installs the CH365 driver according to the system prompt, after installs the good hardware correctly, may compile and debug PCI and the DSP correspondence software under the VC environment.
Through the API function compilation and the DSP mutual data exchange procedure, completes the bidirectional interrupt request and the interrupt response, realizes the data to exchange fast.
3.1 CH365 two-way communication procedures
CH365 supports the PC machine procedure take the single byte, a pair of byte (character), four bytes (double word) as the unit carries on the read-write to the I/O port or the memory. In many byte continual read-write operation period, after a CH365 each read-write byte data, automatic the offset address will add l, directional next byte offset address. We may through write to I/0 mouth 00H the data realizes to the DSP application interrupt, DSP after the response interrupt through read the 00H elimination superior machine interrupt. Its procedure is as follows:
3.2 DSP two-way communication procedures
For the convenience observed data transmission result, in this test establishes, DSP writes the space is Ox0400~Ox07FF, reads the space is OxO000~Ox03FF, formerly namely may realize the lK unit read data read in again the lK unit after the DSP procedure, after then, read in the data and PC machine read in the data carried on the comparison. If tallies, then showing data exchange successfully. Figure 3 gives DSP the procedure flow.
Through bidirectional software testing, result demonstration data exchange entirely accurate.
Conclusion
Along with the computer technology and electronic technology’s development, will operate high speed, the function formidable digital signal processor to apply in the motion control, may realize the complex control algorithm and the high accuracy, the high velocity, the multiple spindle linkage function, in the numerical control application, will occupy more and more important status. But fast, the accurate correspondence is this kind of movement controller’s foundation. This article proposed the mailing address, has the perform reliably, the hardware architecture is simple, the low-cost merit, has the good application prospect.
